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Transaksi WSEAS tentang Pemberitahuan Sistem Tenaga Listrik: Pada tahun 2014 dan untuk tahun-tahun depan, frekuensi publikasi dari Jurnal WSEAS disesuaikan dengan model 3939 yang terus diperbarui. Apa artinya ini adalah bahwa alih-alih dipisahkan menjadi isu, makalah baru akan ditambahkan secara terus menerus, yang memungkinkan arus reguler dan waktu publikasi lebih pendek. Makalah akan muncul dalam urutan terbalik, oleh karena itu yang terbaru akan berada di atas. Judul Makalah: Analisis Perbandingan dan Simulasi Komponen Terpilih dari Sistem Tenaga Modern (EPS, PES) dari Pesawat Udara Klasik dan Langsung Semua Electric Aircraftrsquo (MEA AEA) Penulis: Lucjan Setlak, Rafa Kowalik Abstrak: Pekerjaan berkaitan dengan isu-isu modern Arsitektur kekuasaan di bidang sistem tenaga listrik EPS (Electric Power Systems) dan sistem tenaga listrik elektronik PES (Power Electronics Systems), kedua pesawat terbang sipil 39classical39 menyangkut Airbus dan Boeing (A-320, B-767) dan militer Lockheed Martin (F-16), dan juga pesawat sipil yang memiliki listrik sepenuhnya MEA AEA (A-380 dan A-350XWB, B-787) dan pesawat tempur JSF (Joint Strike Fighter) F-35 dan F-22 Raptor. Berdasarkan hal tersebut di atas, penulis melakukan analisis komparatif terhadap sistem ini, dengan penekanan khusus pada pembuatan simulasi komponen sistem individual yang dipilih (EPS, PES) termasuk model matematisnya dalam perspektif yang dinamis. Tujuan utama dari pekerjaan ini adalah untuk mensimulasikan berbagai EPS (motor sinkron) dan pada konverter PES (48-pulsa), menyajikan model matematis mereka dan berdasarkan pada mereka membuat analisis komparatif sistem tenaga maju dengan tren MEA AEA pesawat. Pada bagian akhir, makalah ini menyajikan kesimpulan utama yang timbul dari analisis dan simulasi komponen arsitektur arsitektur sistem tenaga (EPS, PES) 39classical39 yang terpilih dan yang maju sesuai dengan tren baru 39MEA AEA. Kata kunci: Lebih Banyak Semua Pesawat Listrik (MEA AEA), Sistem Tenaga Listrik (EPS), Sistem Elektronika Daya (PES) WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 40, hlm. 338-346 Judul Kertas: Pada Antarmuka yang Aman Antara Jaringan Kerja Transmisi dan Distribusi Penulis: Pavel Hering, Premysl Vorac, Petr Janecek Abstrak: Makalah ini memperkenalkan interval aliran daya TSODSO yang aman, di mana transisi antara transmisi dan distribusi Jaringan harus aman Produksi listrik yang terus meningkat pada sumber terbarukan intermiten, yang didistribusikan di jaringan, meningkatkan persyaratan untuk memastikan stabilitas jaringan listrik dan juga penyediaan layanan tambahan. Karena kemacetan yang terjadi di jaringan mungkin tidak mungkin menggunakan semua layanan tambahan yang dipertimbangkan. Oleh karena itu, ini menciptakan kebutuhan untuk mendefinisikan sebuah antarmuka untuk berbagi informasi tentang rentang daya yang aman yang dikirimkan antara jaringan transmisi dan distribusi, dimana operasi jaringan aman dapat dijamin. Kata kunci: Jaringan Transmisi, Jaringan Distribusi, Cadangan Daya Tambahan, Keamanan Sistem Tenaga WSEAS Transaksi pada Sistem Tenaga, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 39, hlm. 334-337 Judul Makalah: Model dan Metode Penilaian Resiko Jaringan Distribusi Perkotaan Menimbang Real-time dan Faktor-Faktor Potensial Penulis: Ling Yunpeng, Zhou Mingyu, Wang Jiaren, Ma Guozhen, Zhao Yang, Liu Yong Abstrak: Dalam Agar penilaian akurat terhadap tingkat risiko jaringan distribusi perkotaan, makalah ini menetapkan model penilaian risiko jaringan distribusi dan mengusulkan metode penilaian risiko. Model penilaian risiko jaringan distribusi dibentuk dalam dua aspek, yaitu risiko operasi dan risiko grid. Risiko operasi mencerminkan tingkat risiko keadaan operasi saat ini dari jaringan distribusi, sementara risiko grid mencerminkan potensi risiko akibat cacat struktur grid. Kemudian sistem indeks penilaian risiko yang sesuai dari jaringan distribusi ditetapkan, dan nilai kuantitatif risiko dan peringkat risiko dihitung sesuai dengan nilai indeks. Tingkat risiko jaringan distribusi yang komprehensif diketahui berdasarkan hasil perhitungan di atas, dan bobot variabel dan metode compound logaritma digunakan dalam proses perhitungan. Akhirnya, sebuah contoh numerik menunjukkan bahwa model penilaian risiko yang diusulkan layak dilakukan dan metode penilaian risiko efektif. Model penilaian risiko yang diusulkan telah diadopsi oleh Shenzhen Power Supply Bureau dari China Southern Power Grid, dan efek penerapannya bagus. Kata kunci: jaringan distribusi, penilaian risiko, risiko operasi, risiko grid, nilai kuantitatif risiko. WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 38, hlm. 323-333 Judul Makalah: Sifat Fotometrik dan Listrik Sumber Cahaya Authors: Jiri Vincenec, Martin Zalesak Abstrak: Makalah ini membahas pengaruh peraturan dan suhu terhadap sifat fotometrik dan listrik dari sumber cahaya buatan yang umum Digunakan di bangunan perumahan dan administrasi. Sementara konsumsi energi untuk sistem pencahayaan adalah salah satu bidang penggunaan yang paling penting, adalah mungkin untuk memperbaiki sistem pencahayaan ini dan mengurangi konsumsi energi. Sementara beberapa pendekatan teoritis tersedia hanya beberapa di antaranya dapat digunakan, karena keterbatasan standar yang menentukan kualitas lingkungan bercahaya misalnya, tingkat iluminasi, iluminasi seragam, rendering warna masing-masing warna atau persyaratan silau. Sebagai hasil dari keterbatasan ini, makalah ini membandingkan iluminasi relatif, suhu warna, komposisi spektral dan kurva I-V untuk suhu dan tingkat regulasi yang berbeda untuk menghitung sistem pencahayaan ideal. Untuk pengaturan suhu digunakan ruang iklim, yang menjaga suhu yang dipilih. Untuk regulasi sumber cahaya digunakan aktor regulasi KNX. Pengukuran tidak menunjukkan dampak suhu yang cukup besar pada sifat fotometri atau listrik dari sumber cahaya buatan. Fakta ini akan digunakan untuk perhitungan lingkungan bercahaya yang ideal dengan konsumsi energi ekonomis. Kata kunci: Sumber cahaya, regulasi, suhu, tingkat iluminasi, kurva I-V, komposisi spektral Transaksi WSEAS pada Sistem Tenaga, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 37, hlm. 316-322 Judul Makalah: Model Pasar Listrik Lelang Kombinatorial Berbasis Sisi Satu Authors: Daacutevid Csercsik Abstrak: Model pasar baru berdasarkan lelang kombinatorial untuk perdagangan listrik diperkenalkan, di mana otoritas pusat (CA) Melakukan pelelangan ini terintegrasi dengan operator sistem transmisi (TSO). TSO menerima permintaan dan harga konsumen, dan melakukan pelelangan kombinatorial berbasis arus untuk generator. Untuk setiap subset dari tuntutan yang diumumkan, generator mengevaluasi biaya dan biaya produksi potensial sesuai dengan nilai ini. Selama pelelangan, batas transmisi jaringan kekuatan yang mendasarinya dipertimbangkan secara eksplisit, sehingga kemampuan transmisi digunakan secara efisien. Model ini meningkatkan pemanfaatan karakteristik cekung produksi generator yang paling efisien. Kami menunjukkan bahwa dalam konsep ini TSO termotivasi untuk perluasan jaringan. Kata kunci: Pasar Listrik, Lelang Kombinatorial Transaksi WSEAS pada Sistem Tenaga, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 36, hlm. 309-315 Judul Kertas: Perbandingan Kinerja Pengambilan Umpan Balik Berbasis PSO (K) Controller dengan Pengontrol Integral LQR-PI dan Regulasi Frekuensi Otomatis Penulis: Naresh Kumari, AN Jha, Nitin Malik Abstrak: Pada saat ini Bekerja pengontrol baru yang disebut Particle Swarm Optimization (PSO) berbasis state feedback gain (K) controller telah diusulkan untuk regulasi frekuensi dari dua sistem wilayah dan kemudian kinerjanya dibandingkan dengan pengendali yang dirancang sebelumnya seperti Linear Quadratic RegulatorndashProportional Integral (LQR-PI ) Controller dan Integral controller. Perbandingan kinerja telah dilakukan untuk jaringan sistem tenaga yang terdiri dari dua pembangkit listrik termal yang dihubungkan dengan tie line. Untuk menggunakan metode berbasis kontrol optimal seperti pengontrol LQR-PI dan metode komputasi cerdas seperti pengendali umpan balik berbasis PSO (K), pemodelan keadaan negara dari sistem telah dilakukan. Model fungsi transfer untuk sistem digunakan untuk menemukan respon pengendali Integral. Dalam skema pengendalian generasi efektif, perubahan frekuensi minimum selama variasi beban. Teknik pengontrol umpan balik umpan balik berbasis PSO yang diusulkan telah ditemukan paling efektif untuk meningkatkan respons frekuensi. Kata kunci: Kontrol generasi otomatis, kontrol terpusat, kontrol optimal, kontrol PI, umpan balik negara WSEAS Transaksi pada Sistem Tenaga, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 35, hlm 299-308 Judul Makalah: Interoperabilitas Semantik untuk Perencanaan Operasional untuk Sistem Distribusi Tenaga Listrik Authors: A. Espinosa-Reza, HR Aguilar-Valenzuela, M. Molina-Marin, ML Torres-Espindola, TM Calleros- Torres, E. Granados-Gomez, R. Garcia-Mendoza, CF Villatoro-Hernandez Abstrak: Makalah ini menunjukkan arsitektur Interoperabilitas Semantic berdasarkan Model Informasi Umum (CIM), IEC 61968, IEC 61970 dan standar terkait untuk mengintegrasikan serangkaian Perangkat lunak yang difokuskan pada dukungan keputusan untuk perencanaan operasional Sistem Distribusi Tenaga Listrik, standar yang diadopsi dan perangkat lunak yang diimplementasikan dibahas. Dokumen tersebut menunjukkan beberapa hasil dan manfaat untuk menerapkan arsitektur enterprise untuk Smart Grid di Meksiko. Kata kunci: Interoperabilitas Semantik, Model Informasi Umum (CIM), Smart Grid, Sistem Distribusi Tenaga Listrik (EPDS) WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 34, hlm. 289-298 Judul Kertas: Kontrol Grid Tegangan Rendah melalui Stasiun Pengisian Kendaraan Listrik Authors: Dario De Santis, Gaetano Abbatantuono, Sergio Bruno, Massimo La Scala Abstrak: Mobilitas mobil membutuhkan infrastruktur modern yang andal dan efisien agar Akhirnya mencapai difusi yang lebar. Pada saat yang sama, infrastruktur ini harus diintegrasikan dengan jaringan listrik yang ada dan sering menua: pencocokan ini harus menghadapi beberapa tantangan teknis, terutama pada skenario perkotaan, di mana banyak kendala teknis dan operasional hadir. Selain itu, operasi pengisian kendaraan listrik memerlukan perangkat kontrol yang sangat akurat agar tidak menimbulkan masalah lebih jauh pada sistem distribusi tegangan rendah, namun juga untuk membantu memastikan keamanan jaringan dan kualitas daya. Dalam makalah ini, sebuah metodologi untuk pengoptimalan operasi pengisian EVs, yang bertujuan untuk mengoptimalkan biaya dan debit EVs dalam menanggapi pelanggaran kendala teknis jaringan listrik, kongestasi dan masalah keamanan lainnya di tingkat LV, disajikan. Kata kunci: stasiun pengisian, kendaraan listrik, jaringan distribusi tegangan rendah, grid cerdas, sistem penyimpanan WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 33, hlm. 283-288 Judul Makalah: Pengendalian Aliran Daya pada Sistem Distribusi Tegangan Rendah Authors: Dario De Santis, Gaetano Abbatantuono, Sergio Bruno, Massimo La Scala, Roberto Sbrizzai Abstrak: Sistem distribusi listrik sedang mengalami banyak transformasi radikal, Kebanyakan didorong oleh difusi mendalam unit generasi terdistribusi modern. Fenomena ini meminta solusi teknis yang cerdas dan sangat optimal, untuk mengatasi infrastruktur penuaan dengan tingkat efisiensi operasional yang lebih baik dan memastikan pengelolaan jaringan listrik yang sempurna dan khususnya untuk grid tegangan rendah. Dalam makalah ini, sebuah metodologi untuk mencapai kontrol aliran daya yang cepat dan efisien dan optimalisasi pada sistem distribusi tegangan rendah melalui pemasangan pengontrol aliran daya terpadu (UPFC) disajikan. Hasil numerik pengujian yang telah dilakukan melalui skenario operasi yang berbeda menunjukkan bagaimana perangkat ini dapat diterapkan dengan sukses pada jenis jaringan listrik ini, untuk mengatasi masalah operasional umum seperti kehilangan daya, arus loop dan arus balik. Kata kunci: optimasi generasi terdistribusi, reduksi rugi, grid distribusi tegangan rendah, pengontrol aliran tenaga terpadu WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 32, hlm. 276-282 Judul Kertas: Penempatan Optimal Statcom Menggunakan Algoritma Pencarian Gravitasi untuk Stabilitas Tegangan yang Ditingkatkan Penulis: Tanmoy Deb, Anwar S. Siddiqui Abstrak: STATCOM adalah perangkat FAKTA yang digunakan untuk kompensasi shunt di jalur transmisi untuk mempertahankan bus. Tegangan dalam band toleransi yang ditentukan. Dalam makalah ini, STATCOM digunakan untuk memperbaiki voltase bus dan meminimalkan kehilangan saluran transmisi dengan penempatan optimal di jaringan daya standar. Algoritma Pencarian Gravitasi (GSA) telah mencoba untuk menempatkan STATCOM secara optimal dengan mengoptimalkan kerugian daya dan biaya STATCOM. GSA menghasilkan solusi kualitas yang baik mencapai konvergensi yang lebih cepat. Kata kunci: GSA, penempatan optimal STATCOM, kehilangan daya minimum, Biaya pemasangan minimum WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 31, hlm. 271-275 Judul Kertas: Kontrol Kecepatan Motor Induksi yang Disediakan oleh Turbin Angin Dengan Menggunakan ICA Abstrak: Makalah ini mengusulkan perancangan pengontrol Integral Proporsional (PI) menggunakan Algoritma Kompetitif Imperialis (ICA) untuk mengendalikan kecepatan Sebuah Motor Induksi (IM) yang diberi makan dari turbin angin. Turbin angin berperan sebagai penggerak utama ke generator DC yang terhubung. Pulse Width Modulation (PWM) digunakan untuk mendapatkan tegangan AC tiga fasa dari output generator DC. Masalah disain pengontrol kecepatan yang diusulkan ditetapkan sebagai masalah optimasi. Aula diadopsi untuk mencari parameter pengontrol optimal dengan meminimalkan fungsi tujuan domain waktu. Perilaku ICA yang diusulkan telah diestimasi dengan perilaku Zeigler-Nichols (ZN) dan Genetic Algorithm (GA) konvensional untuk membuktikan efisiensi superior ICA yang diusulkan pada pengendali PI tuning. Selain itu, perilaku pengendali yang diusulkan telah diperkirakan sehubungan dengan perubahan kecepatan turbin angin dan torsi beban. Hasil simulasi mengkonfirmasi kinerja pengontrol PI optimal berdasarkan ICA dibandingkan dengan pengontrol PI yang optimal berdasarkan GA dan yang konvensional pada berbagai kondisi operasi. Kata kunci: Algoritma Genetika, Algoritma Kompetitif Imperialis, Motor Induksi, Kesalahan Absolut Waktu Integral, Kontrol Kecepatan, Turbin Angin WSEAS Transaksi pada Sistem Tenaga, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 30, hlm 261-270 Judul Makalah: SHE PWM dalam Konverter Matriks Tahap Tunggal Menggunakan Algoritma Genetika Berfungsi dan Teknik Optimasi Partikel Swarm Authors: P. Subha Karuvelam, M. Rajaram Abstrak: Dalam makalah ini selektif harmonisa eliminasi pulsa lebar Modulasi (SHEPWM) dengan menggunakan teknik Genetic Algorithm Genetika Alami (RGA) dan Particle Swarm Optimization (PSO) untuk konverter matriks fase tunggal dikembangkan dan dibahas. Dalam teknik ini, fungsi objektif dioptimalkan untuk sudut switching optimal. Frekuensi switching tetap dan sama dengan frekuensi output. Fungsi tujuan dimodifikasi untuk memperbaiki faktor daya masukan dari konverter matriks fase tunggal. Untuk memverifikasi efisiensi algoritma ini, konverter daya telah disimulasikan dalam MATLABSIMULINK dan hasil yang diperoleh dilaporkan. Analisis FFT terhadap bentuk gelombang keluaran simulasi menunjukkan keefektifan metode yang diusulkan. Kata kunci: Konverter matrik Single Phase, Penghambatan Harmomun Selektif, Modulasi Lebar Pulse, Algoritma Genetika Kritis, Optimasi Partikel Swarm, Distorsi Harmonik Total WSEAS Transaksi pada Sistem Tenaga, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Seni. 29, hlm. 251-260 Judul Kertas: Kualitas Unified Quality Conditioner: Solusi Konverter Matriks Tidak Langsung Penulis: MP Alves, T. Geury, SF Pinto Abstrak: Parameter Power Quality (PQ) seperti nilai tegangan RMS, Total Harmonic Distortion (THD), dan Power Factor (PF) adalah topik utama yang harus dipertimbangkan dalam kaitannya dengan beban sensitif ke grid. Dalam makalah ini, Unified Power Quality Conditioner (UPQC) yang didasarkan pada Indirect Matrix Converter (IMC) diusulkan untuk menangani beberapa masalah PQ sebagai mitigasi harmonisa tegangan dan kompensasi sags dan pembengkakan saat memasok beban sensitif. Selain itu, memungkinkan mitigasi harmonisa arus grid di Point of Common Coupling (PCC). Kontrol konverter dilakukan dengan menggunakan metode kontrol mode geser, terkait dengan representasi vektor ruang-negara, yang memungkinkan waktu respon yang cepat terhadap gangguan pada grid. Seluruh sistem diuji dalam perangkat lunak MATLAB Simulink, dan hasil yang diperoleh menunjukkan bahwa ia menjamin perbaikan PQ di PCC. Kata kunci: Kualitas Daya, Kondisioner Mutu Unified Power, Konverter Matriks Tidak Langsung, Kontrol Mode Sliding Transaksi WSEAS pada Sistem Tenaga, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 28, hlm. 244-250 Judul Makalah: Kontribusi Integrasi Perangkat TCSC dan Peternakan Angin pada Sistem Tenaga Listrik Authors: Adjoudj Labiba, Lakdja Fatiha, Gherbi Fatima Zohra Abstrak: Pembangkitan listrik dari tenaga angin telah mendapat perhatian dan integrasi yang cukup besar. Peternakan angin berdasarkan generator induksi double fed (DFIG) mungkin memiliki dampak signifikan pada operasi sistem tenaga. Makalah ini menganalisis dan membandingkan penggabungan peralatan pertanian angin dan perangkat Sistem Transmisi AC yang Fleksibel (FACTS) dan dampaknya pada sistem uji bus IEEE-9 dan IEEE-30. Jaringan barat-Aljazair (2012) juga dipilih untuk studi dan kasus yang berbeda telah disimulasikan di Toolbox Analisis Daya Sistem MATLAB. Oleh karena itu, kita harus memilih di antara perangkat FACTS, yang memiliki aplikasi spesifik seperti mengendalikan aliran daya, Kompensor Seri terkontrol tiruan (TCSC) adalah pilihan terbaik untuk mengendalikan aliran daya yang tepat dan akibatnya pengurangan daya aktif dan reaktif hilang. Hasil simulasi menunjukkan dengan jelas pengaruh alat bertenaga angin dan TCSC terhadap kualitas daya sistem tenaga listrik. Kata kunci: Sistem Tenaga, TCSC, pembangkit tenaga angin, DFIG, analisis aliran daya, Kotak Analisis Daya Sistem WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 27, hlm. 232-243 Judul Kertas: Desain Filter Analog untuk Pengurangan Harmonic dalam Sistem Konversi Energi Angin Authors: Vikas Kumar Sharma, Lata Gidwani Abstrak: Saat ini Harmonika adalah perhatian Power Quality yang utama bagi para insinyur sistem tenaga. Sistem tenaga multi komponen, kompleks dan dinamis memiliki masalah harmonisa yang serius yang membuat sistem tidak linier. Harmonisa dalam sistem konversi energi angin terutama disebabkan oleh efek pemuatan non-liner dari konverter elektronika daya dan beban non-liner. Makalah ini menyajikan kombinasi filter analog yang efisien untuk pengurangan harmonis sistem konversi energi angin terintegrasi grid dengan menggunakan Permanent Magnet Synchronous Generator (PMSG). Tujuan utama kombinasi filter analog adalah mengurangi Total Harmonic Distortion (THD) pada bus yang berbeda. Berbagai kombinasi diambil dengan menggunakan berbagai filter analog dan metode perancangan. Kombinasi ini digunakan pada bus 575V, 25 KV, 120 KV dan hasilnya diambil selama kondisi normal dan rusak. Hasilnya dianalisis untuk kesalahan yang berbeda pada bus 575V dan kombinasi terbaik disarankan pada bus 575V, 25 KV, 120 KV. Kata kunci: Sistem Konversi Energi Angin, filter analog, reduksi harmonik, Pengurangan Harmonic Reduction (THD) Total, Permanent Magnet Synchronous Generator (PMSG) WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Seni. 26, hlm. 220-231 Judul Makalah: Pemodelan Geometrik Sistem Fotovoltaik Berkonsentrasi Rendah Authors: Ionel Laurentiu Alboteanu Abstrak: Makalah ini menyajikan aspek untuk meningkatkan produksi energi sistem fotovoltaik dengan memusatkan radiasi matahari dan orientasi modul fotovoltaik. Untuk memfokuskan sinar matahari pada permukaan fotovoltaik dan meningkatkan energi yang diserap, sistem fotovoltaik surya konsentrasi menggunakan elemen optik yang dapat ditarik (biasanya lensa Fresnel) atau elemen reflektif (biasanya cermin). Sistem pemompaan fotovoltaik bertujuan untuk mengurangi biaya mengenai permukaan fotovoltaik dan menggantinya dengan bahan optik. Masalah desain geometrik disajikan untuk sistem ini yang disesuaikan dengan kondisi lokasi geografis tertentu. Makalah ini dimulai dengan pemodelan sudut panel photovoltaic yang spesifik dan diakhiri dengan prototipe sistem fotovoltaik berkonsentrasi rendah (LCPV). Hasil simulasi menunjukkan bahwa panjang tambahan menurun dengan sudut yang terbentuk antara modul cermin dan fotovoltaik x, dan meningkat dengan sudut kejadian h, yang berarti dengan durasi langkah orientasi. Juga, rasio konsentrasi meningkat dengan kenaikan sudut x. Agar tidak kelebihan berat badan struktur pendukung sistem LCPV sudah ada bahan yang dimanfaatkan dengan bobot ringan. Kata kunci: photovoltaic (PV), sistem pelacakan, photovoltaic berkonsentrasi rendah, pemodelan, desain, geometri WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 25, hlm. 210-219 Judul Makalah: Konverter yang Dapat Dikonfigurasi untuk Penilaian Kinerja Pengubah Daya bertingkat Cascaded Authors: Luis David Pabon, Edison Andres Caicedo, Jorge Luis Diaz Rodriguez, Aldo Pardo Garcia Abstrak: Makalah ini menyajikan pengembangan konfigurasi yang dapat dikonfigurasi. Konverter, dirancang dan dibangun untuk evaluasi beberapa konfigurasi konverter daya bertingkat H-jembatan bertingkat dengan sumber DC tunggal dan sub-topologi sumber DC yang terpisah. Konverter dapat dikonfigurasi dalam topologi simetris dan asimetris dan kisaran level tegangan dibatasi oleh empat perangkat keras H-jembatan. Konverter juga bisa diatur untuk mendapatkan modulasi dari 3 level dan sampai 81 level. Untuk mengonfigurasi konverter, antarmuka pengguna grafis MATLABreg dikembangkan untuk memudahkan perubahan topologi dan memilih jumlah level voltase dan sudut switching. Ini juga memungkinkan pengoptimalan modulasi dengan beralih sudut melalui algoritma genetika. Data antarmuka dikodekan dan dikirim ke FPGA yang mengendalikan konverter multilevel yang dapat dikonfigurasi. Kata kunci: Konverter daya, Multilevel converter, PWM, FPGA, optimasi, algoritma genetika WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 24, hlm. 199-209 Judul Makalah: Desain Pengendalian MPPT Sistem Pendukung Motor DC Generator yang Dimiliki Berdasarkan Algoritma ABC Penulis: AS Oshaba, ES Ali, SM Abd Elazim Abstrak: Pelacakan Titik Daya Maksimum (MPPT) Sistem telah diusulkan untuk sistem pompa motor PV-DC dengan merancang dua pengendali PI. Yang pertama digunakan untuk mencapai MPPT dengan memantau voltase dan arus dari susunan PV dan mengatur siklus konverter DC DC. Pengontrol PI kedua dirancang untuk mengendalikan kecepatan motor seri DC dengan mengatur voltase yang diumpankan ke motor seri DC melalui konverter DCDC lain. Masalah desain yang diusulkan MPPT dan speed controller diformulasikan sebagai masalah optimasi yang dipecahkan oleh Artificial Bee Colony (ABC) untuk mencari parameter optimal pengendali PI. Hasil simulasi menunjukkan validitas teknik yang diajukan dalam mengantarkan MPPT ke sistem motor pompa motor seri DC di bawah kondisi atmosfir dan melacak kecepatan referensi motor seri DC. Selain itu, kinerja algoritma ABC yang diusulkan dibandingkan dengan Genetic Algorithm (GA) untuk berbagai gangguan untuk membuktikan ketahanannya. Kata kunci: Sistem Photovoltaic, Algoritma Optimalisasi, Pelacakan Titik Daya Maksimum, Pengendali PI, Kontrol Kecepatan, Sistem Motor Pompa Seri DC Transaksi WSEAS pada Sistem Tenaga, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 23, hlm. 190-198 Judul Kertas: Peningkatan Konduktivitas dan Kapasitas Pertukaran Ion dari Membran Chitosan melalui Modifikasi dengan Aplikasi Lithium Polymer Lithium Authors: SN Asnin, Wahab, D. Permana, LO Ahmad, SH Sabarwati, LOAN Ramadhan Abstrak : Modifikasi membran kitosan menggunakan lithium telah dikembangkan. Selaput kitosan dibuat dari beberapa tingkat deasetilasi kitosan. Pengaruh tingkat deasetilasi terhadap sifat konduktivitas ion membran chitosan, pengaruh konsentrasi membran chitosan-lithium dan kemampuan konduktivitas ionik sebagai polimer elektrolit untuk aplikasi baterai polimer lithium dipelajari. Membran dibuat dengan metode penguapan pelarut. Spektroskopi transformasi-inframerah Fourier menunjukkan puncak pada 1573,8 cm-1 sesuai dengan interaksi ionik antara garam litium dengan kelompok NH2 dari kitosan. Analisis mikroskop elektron pemindaian menunjukkan kepadatan pori dan kekakuan mikrostruktur membran kitosan yang tinggi, sedangkan membran chitosan-litium memiliki gugus yang mengindikasikan pengendapan garam litium nitrat pada rantai polimer kitosan. Kapasitas serapan air dari membran chitosan-lithium lebih tinggi daripada membran kitosan. Analisis kekuatan tarik menunjukkan bahwa membran chitosan-litium lebih elastis daripada membran kitosan. Konduktivitas membran kitosan dan kapasitas pertukaran ion adalah 1,70 x 10-2 S.cm-1 dan 2,11 meq.g-1, sementara konduktivitas setelah menambahkan garam litium meningkat menjadi 8,53 x 10-2 S.cm-1 dan 3,16 meq.g -1, masing-masing. Hasil penelitian menunjukkan bahwa modifikasi kitosan dengan penambahan garam litium meningkatkan nilai konduktivitas ionik membran dan nilai kapasitas pertukaran ion. Ini membran elektrolit polimer padat memiliki potensi untuk digunakan sebagai elektrolit polimer dalam baterai lithium. Kata kunci: baterai, kitosan, konduktivitas, deasetilasi, kapasitas tukar, litium, membran WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 22, hlm. 183-189 Judul Kertas: Luka Rontok dan Melontar pada Sepeda Motor Teenage-Crash Penulis: Filippo Carollo, Vincenzo Naso, Gabriele Virzirsquo Mariotti Abstrak: Studi tentang cedera yang disebabkan oleh kecelakaan sepeda motor remaja dilakukan pada kertas ini. Hasil kecelakaan dengan tiga kendaraan: sedan, SUV dan Pick up dibandingkan. Tiga posisi berbeda dianalisis: posisi depan, belakang dan lateral. Cedera pada kepala pengendara sepeda diperiksa dengan kriteria HIC, seperti yang ditunjukkan oleh peraturan. Perbandingan antara hasil simulasi Pick up, SUV dan sedan, menyimpulkan bahwa cedera kepala lebih berbahaya untuk dampak Pick-up daripada SUV atau sedan, namun hanya dengan kecepatan lebih tinggi dari 40 km. Pengendara sepeda remaja ini lebih cenderung mengalami cedera pada bagian dada di belakang berimbas dengan sedan, karena nilai 3 ms tetap diatas nilai yang didapat dengan SUV dan Pick up. Tidak seperti Pick up yang bisa menyebabkan luka yang lebih besar pada dada di bagian depan dan samping akibat tingginya ketinggian dari tanah. Massa kendaraan tidak terlalu penting, tapi hanya dengan kecepatan rendah. Pertimbangan dibuat bahwa pengendara sepeda remaja memiliki kesempatan lebih baik untuk bertahan dalam tabrakan dampak depan daripada pejalan kaki orang dewasa, karena nilai HIC tetap konsisten di bawah nilai yang ditentukan. Perbandingan lebih lanjut dilakukan antara titik impak dari ketiga kendaraan yang menyimpulkan bahwa baik bentuk kap mesin maupun bagian depan bagian depan harus dipelajari dengan hati-hati untuk mengurangi kerusakan pada pengendara sepeda dan pejalan kaki. Akhirnya jarak lempar dihitung dan dibandingkan dengan data literatur, menyimpulkan bahwa keduanya sangat bergantung pada posisi relatif. Kata kunci: sepeda motor remaja, dampak kendaraan, (AIS4) cedera, HIC, 3ms, jarak lempar, biomekanik WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 21, hlm. 171-182 Judul Kertas: Analisis Kemampuan dan Batas Torsi Pengoperasian Motor Traksi AC pada Kereta Listrik High-Speed ​​Berkelanjutan Authors: Cornelia A. Bulucea, Doru A. Nicola, Marc A. Rosen, Carmen A Bulucea Abstrak: Keberlanjutan sarana transportasi kereta api berhubungan baik dengan efisiensi energi yang tinggi dan untuk mengurangi dampak lingkungan selama semua tahap kehidupan (yaitu, produksi, penggunaan dan akhir masa pakainya). Telah diterima secara luas bahwa kinerja lingkungan dari operasi motor traksi terkait erat dengan efisiensi konversi energinya. Sejalan dengan gagasan ini, operasi motor listrik traksi yang berkelanjutan di sistem perkeretaapian merupakan tujuan penting saat ini dalam pengembangan lokomotif dan kereta api dengan kecepatan tinggi dan tinggi. Saat ini, kereta listrik kecepatan tinggi kebanyakan bekerja dengan motor induksi tiga fasa atau motor sinkron tiga fasa sebagai motor traksi. Dua jenis mesin listrik memiliki efisiensi yang berbeda pada titik operasi yang berbeda, dan mengalami perbedaan sehubungan dengan keamanan, kecepatan dan kekuatan, penggunaan energi dan efisiensi exergi. Isu penting yang menghubungkan aspek keberlanjutan ini adalah torsi elektromagnetik yang dikembangkan oleh motor traksi listrik, dengan mempertimbangkan bahwa kisaran kecepatan torsi operasi yang luas yang dibutuhkan untuk kendaraan kereta api listrik memberikan batasan yang signifikan untuk mencapai efisiensi motor traksi yang tinggi. Untuk memberikan gambaran umum tentang kinerja teknis dan lingkungan dari operasi kereta listrik yang berkelanjutan, analisis terperinci dilakukan dari kemampuan torsi elektromagnetik motor listrik AC yang digunakan sebagai motor traksi di lokomotif modern dengan daya tinggi dan kecepatan tinggi. Hasil kerja ini dapat membantu dalam meningkatkan kriteria utama untuk mengoptimalkan operasi efisiensi tinggi dari sistem traksi kereta api listrik yang berkelanjutan. Kata kunci: Sistem perkeretaapian listrik, torsi elektromagnetik, exergi, kereta api berkecepatan tinggi, motor induksi, kelestarian, motor sinkron WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 20, hlm. 156-170 Judul Makalah: Suatu Pendekatan Menuju Peramalan Beban Jangka Panjang Real Time Menggunakan Model Indeks Abu-Abu untuk Kerangka Grid Smart Penulis: Sreenu Sreekumar, Jatin Verma, Sujil A. Rajesh Kumar Abstrak: Peramalan beban jangka pendek (STLF ), Yang bertujuan untuk memprediksi beban sistem selama selang waktu satu hari atau satu minggu, memainkan peran penting dalam pengendalian dan penjadwalan operasi sistem tenaga. Most existing techniques on short term load forecasting try to improve the performance by selecting different prediction models. However, the performance also rely heavily on the quality of training data. Although the grey forecasting model has been successfully adopted in various fields and has demonstrated promising results. This paper proposes three short term load forecasting models based on Grey System theory, namely Grey One Index Model (GM(1,1)), Grey Two Index Model using previous year similar day values as input along with previous hour values (GMY (1,2)) and Grey Two Index Model using previous day values as input along with previous hour values (GMD (1,2)) respectively. As shown in the results, the Grey model and its optimized models can increase the existing prediction accuracy. These models have a potential to be used for real time forecasting in smart grid network due to their negligible processing time. Keywords: Short Term Load Forecasting, Grey One Index Model, Grey Two Index Model WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 19, pp. 147-155 Title of the Paper: To Reduce Impact of the Variation of Power from Renewable Energy by Using Super Capacitor in Smart Grid Authors: Amam Hossain Bagdadee Abstract: In the production of renewable energy, maximum power point tracking (MPPT) is always expected .The amount of regeneration energy sources in the network integration of infinite energy, mainly due to changes in the flow of energy. From these sources, in order to ensure the quality of power, in the case of cable resistance, and striking which can be applied mainly AC voltage from high-quality, energy storage, and a significant level to inject energy. On the other hand, this is not a useful resolution. In this article, the energy storage super capacitors have been proposed to be used as the main power source to obtain the time needed to support demand management to work properly (the energy, as the infrastructure, installation via ICT). As a result, it is possible sources. Keywords: Connection and control of the production of renewable energy, converter DC-DC, integrated system, Super Capacitor WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 18, pp. 139-146 Title of the Paper: Wavelet Based Multi-Terminal Transmission Line Protection with MicroGrid Authors: S. Chandra Shekar, G. Ravi Kumar, S. V. N. L. Lalitha Abstract: This paper introduces a novel protection scheme for protecting multi-terminal transmission system combined with microgrid comprises of wind, solar, fuel cell energy sources.Microgrids provide clear economic and environmental benefits for end-customers, utilities and society. However, their implementation poses great technical challenges, such as a protection of microgrid and transmission system. Protection must respond to both utility grid and microgrid faults. The major challenges are a protection system for microgrid which must respond to main grid as well as microgrid faults. After the microgrid is model is developed and it is connected to an equivalent multi terminal transmission system. Wavelet Multi Resolution Analysis is used for detection, classification and location of faults on multi terminal transmission system as well as microgrid resources.The proposed algorithm is tested and it is proved for the detection, classification of faults on transmission system with microgrid which is almost independent of fault impedance, fault inception angle and fault distance of feeder line. Keywords: Microgrid protection, inverter-interfaced microgrids, islanded microgrid WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 17, pp. 133-138 Title of the Paper: The Role of PSO Meter Placement in Distribution State Estimation Abstract: Optimal meter placement with state estimation plays a major role in monitoring and controlling of Distribution System. The objective of this work is to optimize the number of necessary measurements and Remote Terminal Units, subject to the constraints of the system observability requirements for best voltage estimation. A global optimization algorithm and Particle Swam Optimization is proposed to fulfil the requirement. The parameter values are estimated using the Hybrid Artificial Neural Network based state estimation technique of injecting pseudo measurements at un-metered buses. The algorithm is simulated for IEEE and Indian standard bus distribution systems and the results are presented. The effectiveness and flexibility of PSO are demonstrated by validating the results with Mathematical techniques and the effectiveness of estimator. Keywords: Branch and Bound technique, Meter Placement, Particle Swarm Optimization, Power Distribution Systems, State Estimation WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 16, pp. 125-132 Title of the Paper: Optimization of droop setting using Genetic Algorithm for Speedtronic Governor controlled Heavy Duty Gas Turbine Power Plants Authors: M. Mohamed Iqbal, R. Joseph Xavier, J. Kanakaraj Abstract: Biomass is identified as one of the major renewable energy sources for electrical power generation. Heavy duty gas turbine engines are preferred for clean and efficient power generation. An extensive literature survey reveals that the governor droop setting of the heavy duty gas turbines varies from 2 percentage to 10 percentage. But it needs to be optimized for analyzing the dynamic response of heavy duty gas turbine plants in grid connected operation. An attempt has been made in this paper to optimize the speedtronic governor droop setting of all heavy duty gas turbine plants ranging from 18.2MW to 102.6MW using genetic algorithm. Step response of all heavy duty gas turbine plants with the genetic algorithm based droop setting are obtained using MATLABSimulink. On comparing the simulation results based on all time domain specifications and performance index criteria, it is witnessed that the genetic algorithm based droop setting yield optimal transient and steady state responses than the previous findings using SYSTAT software. Therefore the genetic algorithm based droop setting is identified as the optimal droop setting for all heavy duty gas turbine plants in grid connected operation. Keywords: Biomass Power, Heavy Duty Gas turbine, Optimal droop setting, Genetic Algorithm, Simple cycle operation, Simplified Model, Single shaft turbine, Speedtronic Governor, SYSTAT WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 15, pp. 117-124 Title of the Paper: Hybrid Distributed State Estimation Algorithm with Synchronized Phasor Measurements Authors: Camilo A. Villarreal, Jorge W. Gonzaacutelez, Gabriel J. Lopez, Idi A. Isaac, Hugo A. Cardona Abstract: This paper proposes a hybrid distributed state estimation algorithm with synchronized phasor measurements. The implementation is easy since it initially uses a conventional or traditional state estimation and then adds a non-iterative second linear step calculation, which can be implemented by software without hardware investments. Distributed algorithm accuracy was verified in a well-known power system. Even though it was a little less than the state estimation made to the complete system, it offers a faster computation. Hence, for applications that require real-time awareness of the power system, the distributed scheme results are a great alternative that can significantly reduce the bandwidth requirements, like time delays in the processes involved in the supervision and control of the power system. The proposed algorithm makes use of a central coordinator and assumes that each area of the system has at least one synchronized phasor measurement that allows finding the synchronization angles with respect to the angular reference of the system. Keywords: State Estimation, Distributed State Estimation, Hybrid State Estimation, PMU, SCADA, Synchronized Phasor Measurements WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 14, pp. 111-116 Title of the Paper: Evolutionary Optimization Algorithms in Designing a UPFC Based POD Controller Authors: Anwar Haider, Ali Al-Mawsawi, Ahmed Al-Qallaf Abstract: This paper investigates the design of a unified power flow controller (UPFC) based power oscillations damping (POD) controller using evolutionary optimization algorithms (EA). It introduces two optimization algorithms: biogeography based optimization (BBO) and particle swarm optimization (PSO), that are used to design the POD controllers. The optimal set of parameters for the controllers are found using two different objective functions, eigenvalue based objective function and time based objective function, over a wide range of system operating points in order to obtain a robust controller. The obtained controllers are then verified and tested over four different loading conditions of the system with different system parameter uncertainties introduced in each case. Keywords: Power system oscillations, unified power flow controller, biogeography based optimization, particle swarm optimization, evolutionary optimization algorithms, FACTS WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 13, pp. 100-110 Title of the Paper: Hybrid Carrier PWM Strategies for Three Phase H-Bridge Multilevel Inverter Authors: C. R. Balamurugan, S. P. Natarajan, R. Bensraj, T. S. Anandhi Abstract: In this paper, hybrid modulation methods suitable for H-bridge MLI is discussed. The results of experimental work using dSPACE system only are presented for three phase five level cascaded type inverter. Different hybrid carrier PWM (Pulse Width Modulation) strategies using sinusoidal reference, third harmonic injection reference, 60 degree reference and stepped wave reference for the chosen inverter are initially developed using SIMULINK. Strategies developed are then implemented in real time using dSPACERTI. The five level output voltages of the chosen MLI (Multi Level Inverter) obtained using the dSPACE system based PWM strategies and the corresponding THD (Total Harmonic Distortion) and VRMS (fundamental) are presented and analyzed. It is seen that PSVF (Phase shift Variable Frequency) and PSPD (Phase Disposition) for sinusoidal reference. PSVF and COPS for THI (Third Harmonic Injection) reference, PDVF for 60 degree reference and APODPD and PDVF for stepped wave provides output with relatively low distortion. It is found that COPD with sine reference, APODCO and COPS PWM with THI reference, COPD PWM with 60 degree reference and APODCO and COPD PWM with stepped wave reference perform better since it provides relatively higher fundamental RMS output voltage and relatively lower stress on the devices. The simulation and hardware results closely match with each other. Keywords: Hybrid, THD, DSPACE, RTI, Control desk, PWM, Driver circuit WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 12, pp. 90-99 Title of the Paper: Congestion Management Using Multi-Objective Grenade Explosion Method Authors: S. Surender Reddy Abstract: The operational aspects of power systems pose some of the most challenging problems encountered in the restructuring of electric power industry. This paper focuses on Congestion Management within an Optimal Power Flow (OPF) framework in the deregulated electricity market scenario. The conventional OPF problem is modified to create a mechanism that enables the market players to compete and trade, and simultaneously ensures that the system operation stays within the security constraints. The centralizedpool and bilateral dispatch functions of an Independent System Operator (ISO) are considered in this paper. Here, Multi-Objective Grenade Explosion Method (MO-GEM) based approach is presented to formulate as multi-objective optimization problem with competing fuel cost and system loss minimization as objective functions. The proposed approach is tested on IEEE 30 bus system. The simulation results revealed the capabilities of the proposed MO-GEM approach to generate well distributed Pareto optimal non-dominated solutions of multi-objective generation cost and transmission loss minimization. Keywords: Congestion Management, Optimal Power Flow, Electricity Markets, Evolutionary Algorithms WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 11, pp. 81-89 Title of the Paper: Sensorless Fuzzy Sliding Mode Speed Controller for Induction Motor with DTC Based on Artificial Neural Networks Authors: Sarra Massoum, Abdelkader Meroufel, Abderrahim Bentaallah, Fatima Zohra Belaimeche, Ahmed Massoum Abstract: The objective of this work is to develop a Fuzzy Sliding Mode Speed Controller and to replace the conventional selector switches of the voltage inverter by a selector based on Artificial Neural Networks (ANNs) for the induction motor drive. The Direct Torque Control (DTC) is known to produce quick and robust response in AC drive system. However, during steady state, torque, flux and current ripple occurs. An improvement of electric drive system can be obtained using a DTC method based on ANNs which reduces the torque and flux ripples. The rotor speed and stator flux are estimated by the model reference adaptive system (MRAS) scheme which is determined from measured terminal voltages and currents. The speed loop is carried out by a Fuzzy Sliding Mode Controller (FSMC) giving high performance and robustness to the drive system. The MATLAB SIMULINK is used to perform the simulation. The simulated results of this method are discussed and compared with conventional DTC. Keywords: DTC, induction motor, MRAS, speed FSMC, ANNs, torque ripple minimization WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 10, pp. 72-80 Title of the Paper: Economic Analysis of Energy Storage System Integration with a Grid Connected Intermittent Power Plant, for Power Quality Purposes Authors: Alejandro Nieto, Vasiliki Vita, Lambros Ekonomou Abstract: The increasing integration of grid scale intermittent power plants, like wind farms, is impacting negatively the stability of the interconnected power grid affecting the load factor of the intermittent power plant. Energy storage systems (ESS) are being considered as a potential solution for this problem since it can increase the power being exported to the grid by the wind farm, making it more stable, and therefore guarantying its economic feasibility. In this paper an economic study is carried out to analyze the economic feasibility for the integration of flywheel energy storage systems (FESS) with a wind power plant. It was concluded that the installation of the FESS is only feasible with the government subsidy in renewable energy projects, if considering that installation costs would not be reduced more than 10 of the estimated value. In addition, the integration of ESS would potentially improve the load factor of the power plant by increasing the load factor and therefore, make the project more profitable from an independent power producer perspective. Keywords: Energy Storage Systems, Economic Study, Renewable Energy WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 9, pp. 65-71 Title of the Paper: Harmonic Assessment in Jordanian Power Grid Based on Load Type Classification Authors: Eyad Almaita Abstract: The demand of efficient power converters lead to the proliferation of nonlinear loads in the power system. These nonlinear loads cause a serious problems that affect the power quality in both transmission and distribution systems. One of the major Power quality problems is Harmonic pollution. Understanding and quantifying the harmonics level in electrical power grid are crucial before proposing any successful method for mitigating harmonics problems in the grid. In this paper, the harmonics level in Jordan Low-Voltage Electrical Power Grid (JLVEPG) is investigated. The loads are divided into five categories. (i) industrial loads, (ii) commercial loads, (iii) hospital loads, (iv) residential loads, and (v) office loads. Assuming each category will inject similar harmonics in the grid, which will facilitate harmonic assessment in the power system. Also, this categorization of the loads will make proposing harmonic mitigation solutions much easier. A field measurement for the major electrical units (Voltages, currents, and power) in JLVEPG is carried out for different locations in multiple cities. These measurements are followed by data analysis techniques in order to identify the total harmonic distortion (THD), the most dominant harmonic in each load category, and the harmonic power as a ratio to the active power. Keywords: Power quality, harmonics, distortion, harmonic assessment, Jordan, THD WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 8, pp. 58-64 Title of the Paper: Research on the Numerical Accuracy of Equipotential Ground Model Based on Method of Moment Authors: Junyang Ma, Zaijun Wu, Minqiang Hu, Xiaobo Dou, Yurong Wang, Hao Chen Abstract: In numerical calculations of grounding grid based on the method of moment, accurately calculation of the resistance matrix is an important step. The direct numerical integration method, Heppersquos method and Kouteynikoffrsquos method have the most broad influence in the previous publications, and the accuracy of these algorithms require further evaluation. A software for simulating grounding systems has been developed based on the method of moments in this paper, it implements the above several important algorithms. Under the assumption of uniform soil and ignoring the conductor impedance, the calculation results of the above methods and CDEGS are compared, and sources of error are analyzed. Furthermore, since the grounding electrode need to be cut into small segments properly when using the method of moment, the effect of the conductorrsquos different divisions for accuracy is analyzed quantitatively, and the rule of the calculation accuracy of grounding resistance with the change of segment numbers is obtained. After comparison of the above methods in the case study, theoretical analysis and program test reveal the theoretical flaw of the Kouteynikoff39s method. Keywords: Grounding grid, numerical calculation, method of moment, Hepersquos method, Kouteynikoffrsquos method, CDEGS, Numerical Accuracy WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 7, pp. 52-57 Title of the Paper: Forecasting Electricity Price Using Seasonal Arima Model and Implementing RTP Based Tariff in Smart Grid Authors: Hemant Joshi, Vivek Pandya, Chetna Bhavsar, Mitesh Shah Abstract: A Smart Grid has a two-way digital communication system and it encourages customers to actively participate in different types of Demand Response (DR) programs. In the Smart Grid market, both the supplier and broker agent earn profit while distributing the electrical energy. They have to balance the supply and demand during the distribution of energy. They also participate in energy trading to earn more money. To minimize trading risks, forecasting of wholesale electricity prices is necessary. A Real Time Price (RTP) based power scheduling scheme can be implemented effectively in Smart Grid to match supply and demand. In this scheme, Home Energy Controllers (HEC) and Smart Plugs can be used to shift the operation of schedulable load from peak period to off-peak period. To shift the operation of schedulable load during off-peak period, electricity price should be available in advance. In order to have the electricity price in advance, accurate forecasting is needed. Demand and supply depends on so many factors such as weather condition, cloud cover, wind speed, day of the week and festivals. It is difficult to forecast energy prices in such uncertainty. In this work, the best fitted seasonal ARIMA (Auto Regressive Integrated Moving Average) model is identified and used to forecast the next weekrsquos electricity price. This forecasted electricity price helps in deciding the next dayrsquos load pattern and minimizing the trading risk. Algorithms for HEC and Smart Plug are presented in this work to identify the optimized time slots and to allow power to the schedulable appliances during those slots. Keywords: Smart Grid, Demand Response, Real Time Price, Smart Plug, Home Energy Controller, ARIMA WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 6, pp. 43-51 Title of the Paper: A Development of Acoustic Energy Transfer System through Air Medium Using Push-Pull Power Converter Authors: Thoriq Zaid, Shakir Saat, Norezmi Jamal, Siti Huzaimah Husin, Yusmarnita Yusof, S. K. Nguang Abstract: This paper presents a development of Acoustic energy transfer (AET) system through air medium using push-pull power converter. The push-pull converter may operate under zero voltage switching condition at resonance frequency and capable to minimize switching losses. This paper investigates the performance of AET through the air by using ceramic disc ultrasonic transducer, specifically for low power applications. A multiple input-output transducer is also designed in this paper. The simulation and experimental works are carried out and the obtained results are analysed accordingly. Based on the experimental results, the 1.07mW output power is obtained at 40kHz operating frequency. The multiple transceiver design offers 100 efficiency of energy transmission which is 7.24mW output power. Keywords: Contactless Energy Transfer, Acoustic energy transfer, Ultrasonic transducer, Push-pull converter WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 5, pp. 35-42 Title of the Paper: Comparative Evaluation of New FLC Controller Based MPPT for a DC to DC Buck-Boost Zeta Converter Authors: R. Arulmurugan Abstract: A new intelligent technique of tracing the peak power point of a standalone photovoltaic (PV) module using Fuzzy Logic Control (FLC) is presented in this paper which exploits the effects of the characteristic of PV module. Partial shaded and change in weather conditions produces numerous local maximum peak points (MPP), which makes the tracing of the multiple global peak power a challenging task. Furthermost of traditional tracing technique fail to operate correctly under these non-uniform irradiance situations. The real traditional FLC search based maximum power point tracking (MPPT) flops to trace the peak power under partial shaded situations. This paper advances the technique by considering the wide range of search and power ripple so that the designed FLC technique traces maximum power for all the situations. It is tested for dissimilar weather condition through Matlab simulation and verified laboratory experimentally. In this paper, the merits of using a novel FLC is also offered. Three inputs and single output fuzzy rules are developed. From the Matlab simulation outcomes, it is observed that the FLC controlling technique decreases error and it provides rapid reaction to environmentally friendly variations. The competence of the designed technique has closely coordinated with the true maximum power point (MPP) and the successful laboratory experimental results attained with a 100 Watt photovoltaic module specify that the method can be favourably realized for photovoltaic standalone system. Keywords: Maximum Tracking, Photovoltaic, Fuzzy Logic Control, DC to DC buck-boost Zeta converter WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 4, pp. 27-34 Title of the Paper: Optimal Power Flow Using Cuckoo Search Considering Voltage Stability Authors: M. A. Elhameed, Mahmoud M. Elkholy Abstract: Optimal power flow is the most complicated economical problem in power system operation. This is due to the nonlinearity of load flow equations and constraints on voltage, thermal limits and angle and voltage stability. The objective of this problem is to distribute system loads among generators with minimum cost while achieving all equality and inequality constraints. Nowadays, meta heuristic methods are used to solve this problem such as genetic algorithm, particle swarm and tabu search. In this paper Cuckoo search is investigated with additional constraints on voltage stability and output of reactive power compensators. Considering the initial load angles of generators will enhance the transient stability of power system. Results obtained by Cuckoo search are compared to that obtained by genetic algorithm, Tabu search and gradient descent methods. With the same loading conditions and constraints, Cuckoo search based optimal power flow gives less cost compared to these methods. The algorithm is investigated on IEEE 30 bus system. Keywords: OPF, Cuckoo search, voltage stability, reactive power compensators WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 3, pp. 18-26 Title of the Paper: Power Transformer Fault Detection and Isolation Based on Intuitionistic Fuzzy System Authors: Manikandan Pandiyan, Geetha Mani Abstract: Power transformer oil using Dissolved Gas Analysis (DGA) is the most used diagnosis method for power transformer faults. Though various methods have been developed to interpret DGA results, sometimes they fail to determine the faults. Forecasting of the ratios of key-gas in transformer oil is a complicated problem due to its non-linearity and the small amount of training data. This paper presents Intuitionistic Fuzzy System (IFS) to diagnose several faults in a transformer. This proposed approach is recommended for fault transformer diagnosis and the suitable actions to be taken. It has been proved to be a very advantageous tool for transformer diagnosis and upkeep planning. This method is applied to an independent data of different power transformers and various case studies of historic trends of transformer units. This method has been successfully used to identify the type of fault developing within a transformer even if there is conflict in the results of AI technique applied to DGA data. Keywords: Power transformer, DGA, IFS, fault diagnosis WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 2, pp. 10-17 Title of the Paper: Renewable Energy Impact on Power Quality Performances in Modern Electric Grids Authors: Morris Brenna, Federica Foiadelli, Michela Longo, Dario Zaninelli Abstract: The significant increase of the Renewable Energy Sources (RES) has radically transformed the electricity generation system presenting many aspects to be studied and analyzed. RESs such as solar and wind are fluctuating and weather-driven sources, that can introduce consequences for the functioning and the quality of the delivered power to the end users. This paper aims to present a deep research of the impact, in terms of power quality, of the introduction of photovoltaic and wind generation into the Italian electric grid, that covers many different case studies since the variety of its topology depending on the geographical regions. A deep study, based on infield measurements data, of the correlation between power quality, in particular voltage sags, and renewable energy introduction is presented and discussed. Keywords: Power Quality, Voltage Sags, Wind Farm, Photovoltaic System, Renewable Energy WSEAS Transactions on Power Systems, ISSN E-ISSN: 1790-5060 2224-350X, Volume 11, 2016, Art. 1, pp. 1-9 Bulletin BoardRefine DSP companies and products: Click on any vendor to see a listing of DSP related products. The FMC645 is a Digital Signal Processor FMC daughter card based on the Texas Instruments TMS320C6455 device. The FMC645 daughter card is mechanically and electrically compliant with the FMC standard (ANSIVITA 57.1). The card has a high-pin count connector and can be used in a conduction cooled environment. The card is equipped with power supply and temperature monitoring and offers several power-down modes to switch off unused functions and peripheral interfaces. Several Gigabit differential pairs from the FMC connector are used to implement a PCIe and Serial Rapid IO interface between the FMC and the carrier. Many other digital IO interfaces are also made available to the FMC carrier. Because of the use of level translators between the DSP and the FMC connector the FMC645 can fully operate on any VITA 57.1 compliant carrier. A 512 MB DDR2 SDRAM on-board bank directly connects to the DSP thus providing the FMC645 with the memory resources required for demanding signal processing applications. () FM577The FM577 is a low-cost, low-power 65nm FPGA-based board available in the PMC form factor () FM485Dual FPGA Virtex-5 and Virtex-4 with 128 MB DDR2 and 16 MB of QDRII SDRAM Local Memory PMC-X and XMC for high-bandwidth analog conversion DSP processing () FM486Dual FPGA Virtex-5 Virtex-4 with up to 512 MB DDR3 and 8 MB of QDRII SDRAM Local Memory PMC-X and XMC for high-bandwidth analog conversion DSP processing () FM482Dual Xilinx Virtex-4 FPGA Signal Processor PMCXMC () A DSP DAC for high-speed analog signal regeneration and digital signal processing () A DSP ADC for high-speed analog signal capturing and digital signal processing () CPCI381A 3U CompactPCI board providing a powerful platform for high-speed analog signal capturing and digital signal processing () TMS320C32 floating point DSP, running at 60 MHz, delivering 30 MIPS Two simultaneous sampling 12-bit AD channels Programmable sampling rate up to 7.5 Msamplessec Provides a powerful platform for high-speed analog signal capturing and digital signal processing () Two analog input channels are capable of simultaneously sampling at (maximum) 7.5 MSps sampling rate Local software allows enhanced and user-specific signal processing Gain and offset errors are compensated by the DSP CPCI383A 3U CompactPCI board providing a powerful platform for high-speed analog signal (re)generation and digital signal processing () TMS320C32 floating point DSP, running at 60 MHz, delivering 30 MIPS Three high-speed, 16-bit DA channels Analog output rate is software programmable up to 7.5 Msamplessec (using DMA, single channel) Provides a powerful platform for high-speed analog signal (re) generation and digital signal processing () Analog and digital IO () Analog and digital IO () The M393 8-Channel Differential Input ADC M-module is very well suited to be used in applications in which autonomous signal conversion is an issue, as well as in standard mid-range applications () Enabled channels are scanned at maximum rate and conversion results are stored in shared memory A local DSP performs all functionality and user specific functions can be added for customized operation . The M392 16-Channel Common-Mode Input ADC M-module is very well suited to be used in applications in which autonomous signal conversion is an issue, as well as in standard mid-range applications () Enabled channels are scanned at maximum rate and conversion results are stored in shared memory A local DSP performs all functionality like calibration. User specific functions can be added for customized operation . TMS320C32 floating point DSP, running at 60 MHz, providing 30 MIPS () Optimized for low cost, extending the reach of FPGAs further into cost-sensitive, high-volume applications () Customer-defined feature set, industry-leading performance, and low power consumptio Greatly increased density and more features, all at significantly lower cost 150 embedded 18 x 18 multipliers Nios II, StratixInternal clock frequency rates up to 500 MHz and typical performance 250 MHz () Deliver on average 50 faster performance and more than 2x the logic capacity than first-generation Stratix FPGAs Deliver 50x higher multiplier bandwidth than single-chip, standalone digital signal processors The DSP blocks have the flexibility and performance to implement fast, arithmetic-intensive applications such as image processing, wireless communications, military, broadcast, and medical 28-nm Stratix V FPGAsWith the variable-precision DSP block, Alteras Stratix V FPGA can support 8211 on a block-by-block basis 8211 v arious precisions ranging from 9-bit x 9-bit up to single-precision floating point (mantissa multiplication) within a single DSP block () This frees you from FPGA architecture restrictions, allowing you to use the optimum precision at each stage of the DSP data path Increased system performance, reduced power consumption, and reduced architectural constraints Each variable-precision block can be configured at compile time to implement: Dual 18-bit x 18-bit multipliers in the sum or independent modes Up to 680K logic elements (LEs) 2X bigger than Alteras Stratix III family Altera 40-nm devices meet the diverse high-end application needs in a large number of markets such as wireless and wireline communications, military, broadcast, and ASIC prototyping Stratix DSP Development KitA development kit for Texas Instruments DSP development platforms to enable development of FPGA coprocessors () Features a development board with the Stratix EP1S80 device, two 12-bit, 125-MHz AD converters, two 14-bit, 165-MHz DA converters, 64 Mbits of Flash memory, 2 Mbytes of synchronous SRAM, and a connector to Analog Devices AD evaluation boards Includes a cross-platform daughtercard that plugs directly into Texas Instruments high-performance TMS320C6000 and cost-efficient TMS320C5000 DSP development platforms Provides hardware evaluation versions of key DSP intellectual property, including a FIR compiler, infinite impulse response (IIR) filter compiler, as well as Correlator, FFT, Viterbi, and Reed Solomon cores Stratix II FPGAExtensive IP portfolio support () DSP blocks offer higher performance with multiplier, pipeline, and accumulate something missing here Offers more than 142 GMACS of DSP throughput using DSP blocks Delivers 4x the DSP block bandwidth of Stratix devices 8211 up to 370 MHz A DSP development tool with expanded access to Altera IP and support for The MathWorks MATLAB 7SimuLink 6 software () Supports the Atratix II and Cyclone II device families Supports Alteras DSP Meg aCore IP portfolio Includes a color space converter UP core and an edge detection reference design with a two-dimensional filter for video and image processing designs High-speed IO signaling and interfaces () Supports the latest external memory interfaces in dedicated circuitry, including DDR2 SDRAM, RLDRAM II, and QDRII SRAM devices Brings programmable logic functionality and benefits to new applications requiring design security TriMatrix Memory Stratix EP1S80A DSP development board () Included with the Stratix Professional Edition DSP development kit Two 12-bit, 125-MHz AD converters Two 14-bit, 165-MHz DA converters Links MATLABSimulink tools with the Altera Quartus II design software () Fully supports Altera DSP IP Supports Stratix, Stratix II, Cyclone, and Cyclone II families Enables rapid prototyping with Alterathird-party DSP development boards Stratix II Dev. KitDSP development board, Stratix II Edition with a Statix II device () Provides variety of analog and digital IOs 16 MB SDR SDRAM 16 MB Flash 1 MB SRAM 32 MB compact flash memories MATLABSimulink evaluation software DSP BuilderLinks MATLABSimulink tools with the Altera Quartus II design software () Fully supports Altera DSP IP Supports Stratix, Stratix II, Cyclone, and Cyclone II families Enables rapid prototyping with Alterathird-party DSP development boards Cyclone II FPGAIndustrys lowest-cost programmable logic platform for DSP implementation () Offers up to 68,416 LEs of logic density and 1.1 Mb of embedded memory Delivers embedded configurable multipliers for low-cost DSP applications Provides up to 150 18-bit x 18-bit multipliers operating at up to 250 MHz A single-chip microcomputer optimized for digital signal processing and other high-speed numeric processing applications () The EZ-KIT Lite evaluation kit is available for ADIs ADSP-21160x SHARC family of DSPs, as well as the ADSP-2189 M-Series () It provides a cost-effective method for initial evaluation of both of these DSP architectures The ADSP-21160M EZ-Kit Lite kit interfaces to ADIs VisualDSP toolset The ADSP-2189M EZ-KIT Lite kit consists of a stand-alone DSP board with code generation and debug software and facilitates evaluation of the ADSP-218x DSP family, as well as the VisualDSP development environment, which includes a C compiler, assembler, and linker . A 16-bit fixed-point DSP optimized for telecommunications and other high-speed numeric processing applications () Operates at 160 MHz and is capable of 160 MIPS DSP is code compatible with the ADSP-21xx family with increased performance On-chip system interfaces support T1, E1, and H.100-based high-density telephony systems A high-performance DSP capable of delivering MCU control functionality in a single instruction set at 300 MHz sustained performance () An embedded DSP processor integrating two identical Blackfin DSP cores () Enables symmetric multiprocessing (SMP) Performance of 750 MHz and 1500 MMACs (million multiple accumulate operations) per core Each core contains two multiplieraccumulators (MACs), two 40-bit ALUs, four 8-bit video ALUs, and a single barrel shifter An Internet Gateway Processor DSP chip with an architecture capable of performing multiple operations in parallel () A set of three DSP processors in the TigerSHARC family () A TigerSHARC DSP processor () Static sup erscalar architecture that supports 1, 9, 16, and 32-bit fixed point processing High-performance, 600- MHz, 1.67 nsecs instruction rate DSP core 24 Mbits on-chip embedded DRAM internally organized in six banks with user-defined partitioning A 16-bit fixed-point DSP optimized for telecommunications and other high-speed numeric processing applications () A family of six single-chip microcomputers optimized for digital signal processing applications () A 100 MHz SIMD 32-bit fixed-point and floating-point DSP () 1-Mbit of dual-ported, onchip SRAM can be user configured IEEE 784-884 floating-point compliant 14 DMA controller channels support data transfer between internal memory and external memory, external peripherals, host processor, and multiple ports SHARC174 Processors, in its third generation, combine a high-performance fixed- and floating-point processing core with sophisticated memory and IO processing subsystems. () A low-power, single Multiply-Accumulate (MAC), 16-bit fixed point DSP core designed specifically for embedded and highly integrated System-on-Chip (SoC) designs () High frequency 8211 up to 200 MHz 0.13u worst case process Power consumption: Active mode - using full DSP capability Slow mode - clock speed and current consumption, linearly divided, relative to active mode by a user-defined factor and Stop mode - leakage current only High code density using 16-bit instructions width CEVA-X1620 DSPCEVA-X1620 is the first implementation of the CEVA-X DSP family consisting of 16-bit data width and two MAC units () CEVA-X1620 target markets include 3G cellular handsets and Software radio, smart phones PDAs, Video, and Audio processing for mobile devices, VoIP gateways and broadband modems, and home entertainment (Digital TV, HDTV, PVR, HD-DVD) Dual MAC 16-bit fixed point DSP Combination of VLIW and SIMD architecture concepts Available as part of the CEVA-Toolbox Software Development Envi ronment () Project build optimizer: Creates optimized build configurations, simulates and profiles multiple application scenarios based on the customers application and exact system conditions DSP and Communication Libraries: C-callable assembly optimized functions, significantly improve performance and development time of DSP and communication applications Application Profiler: A cycle accurate C-level application and memory subsystem profiler A low-power, high-performance, dual Multiply-Accumulate (MAC), 16-bit, fixed-point DSP core () Integrated, programmable audio platform: DSP core and subsystem Broad range of audio codecs Short time to market Low risk () Robust performance: Low cost - 0.5mm2 for the DSP at 65nm process Low power - 0.5 mW for stereo MP3 decoder Strong technology heritage: Leverages on widely-deployed CEVA-TeakLite technology Audio codecs deployed in key cellular and consumer device markets Single source solution: Reduces risks and solution complexity The AMC-D24AF 4-RF2 is a highly integrated AdvancedMC (AMC) card with two wideband RF transceiver channels. The module22683648482s main processor is the KeyStone2268222162 II architecture-based TCI6638 digital signal processor (DSP)ARM194174 SoC, which includes eight TMS320C66x DSP cores, as well as four ARM Cortex194174-A15 cores for higher layer processing. The module also has two C6678 DSPs, plus a large Xilinx Kintex-7 FPGA. () AMC-D1F1-1200An AdvancedMC module that offers a compact, high-performance DSPFPGA signal processing solution for AdvancedTCA and MicroTCA systems () Texas Instruments TMS320C6455 digital signal processor running at 1.2 GHz and a Virtex-4 FX100 FPGA from Xilinx Optimized for applications requiring high-end signal IO bandwidth in a compact mid-height AMC form factor, such as wireless baseband, image processing, defense, and aerospace Provides a combination of DSP and FPGA resources, with fast and flexible links to external data and over 256 MB of onboard memory A highly integrated AdvancedMC card based on TI22683648482s TCI6636 and TMS320C6678 DSP SoCs plus a large Xilinx Kintex-7 FPGA and 4x4 RF. The AMC-D24A4-RF4 is an extremely high performance ARM, DSP and FPGA based processing card which includes four integrated, flexible, wideband RF transceiver channels. The module is aimed at LTE, LTE Advanced and 5G systems that require MIMO technologies and enables complete RF to Layer 3 wireless basestation functionality to be implemented on a single AdvancedMC card. The module22683648482s main processor is the TCI6636 KeyStone II DSPARM SoC. It includes eight C66x DSP cores, as well as four ARM Cortex2268222162-A15 cores for higher layer processing. The module also has two TMS320C6678 octal C66x core DSPs. All processors are closely coupled via TI22683648482s Hyperlink interface and the Ethernet infrastructure of the card with Serial RapidIO (SRIO) backplane connectivity providing inter-card connectivity. There is also a large Kintex-7 FPGA for additional co-processing and to manage the RF interface FEATURES: 1 Texas Instruments TCI6636 SoC DSP 2 Texas Instruments TMS320C6678 SoC DSPs Each DSP has 8 cores - 24 DSP cores in total 4 RF channels, each supporting FDD or TDD 662MHz - 3.84GHz 20Gbps Gen2 RapidIO to AMC.4 compliant backplane 3x SFP to FPGA, up to 10.3 Gbaud Gigabit Ethernet interface Integrated GPS receiver Double width, full-size AMC card . () The AMC-2C6678L is a high performance DSP card. It is powered by the latest Texas Instruments SoC TMS320C6678 DSPs. The 16 C66x DSP cores are connected together with high speed Hyperlink, PCIe and SRIO links and is ideal for a range of high performance DSP processing applications including image sensor processing, telecomms and stepper control. In addition, it can be used for DSP based acceleration of voice and video applications. The cores operate at 1.25GHz and have the combined power to process 320 GFLOPS and 640 GMACS. The board is supplied with software support libraries and 3L Diamond is fully supported on this platform for advanced multiprocessor code development. CommAgility can support your needs if modifications are required to make this product fit your OEM requirements. FEATURES: 2 Texas Instruments TMS320C6678 DSPs Each DSP has 8 C66x cores operating at 1.25GHz (16 DSP cores total) PCI Express Gen 3 link to AMC.1 compliant backplane with on-board switch 20gbps Gen2 RapidIO to AMC.4 compliant backplane. Full Gigabit Ethernet infrastructure Single width, mid-size AMC card (full-size option available). . () AdvancedMC modules based on the latest high-performance TMS320TCI6616 base station System-on-Chip (SoC) and TMS320C6670 digital signal processor (DSP) from Texas Instruments Incorporated (TI) () The two modules harness the industry-leading power of TIs new devices and add high-speed, flexible IO to deliver solutions for wireless base station and high-performance applications The modules also include a Xilinx LX240T Virtex-6TM FPGA for additional IO and co-processing flexibility The AMC-2C6616 incorporates TIs new CI6616 SoC base station, and is targeted at LTE wireless base station applications, including development, trials and final deployment in the field The AMC-4C6678 is a high performance DSP card. It is powered by the latest Texas Instruments SoC TMS320C6678 DSPs. The 32 C66x DSP cores are connected together with high speed Hyperlink, PCIe and SRIO links and is ideal for a range of high performance DSP processing applications including image sensor processing, telecomms and stepper control. The cores operate at 1.25GHz and have the combined power to process 640 GFLOPS and 1280 GMACS. The board is supplied with software support libraries and 3L Diamond is fully supported on this platform for advanced multiprocessor code development. FEATURES: 4 Texas Instruments TMS320C6678 DSPs Each DSP has 8 C66x cores operating at 1.25GHz (32 DSP cores total) PCI Express Gen 3 link to AMC.1 compliant backplane with on-board switch 20gbps Gen2 RapidIO to AMC.4 compliant backplane. Full Gigabit Ethernet infrastructure Single width, full-size AMC card . () AMC-K2L-RF2The AMC-K2L-RF2 is a low-cost, high performance ARM and DSP based processing card based on TIs TCI6630K2L SoC which includes two integrated wideband RF transceiver channels, all in the compact Advanced Mezzanine Card (AMC) form factor. It is designed to support wireless baseband processing and a 2x2 MIMO air interface in radio test systems, small cells, and UEs for standard or specialised LTE and LTE-Advanced systems up to and beyond Release 10. () VPX-D16A4-PCIEThe VPX-D16A4-PCIE is a rugged high performance DSP and FPGA based card in the compact VITA 65, 3U OpenVPX form factor, with a high speed Gen2 PCI Express (PCIe) interface. () AMC-2C6678The AMC-2C6678 is a high performance signal processing AMC card with 16 DSP cores and FPGA resources. It is powered by the latest Texas Instruments TMS320C6678 DSPs plus a Xilinx Virtex-6 FPGA. It is ideal for a range of high performance DSPFPGA processing appli-cations including telecoms and image processing. An IDT CPS-1848 Gen2 SRIO switch provides a 20Gbps per port Serial RapidIO infrastructure. Now with 1.2GHz DSPs each with 1GB SDRAM. (). CA-AMC-D4F1A single-width AdvancedMC module designed for high-bandwidth, high-performance signal processing, providing DSP and FPGA processing and 10 Gbps Serial RapidIO () A DSP board for math-intensive multichannel telephony applications like Internet voice and fax gateways () Delivers up to 7200 MIPS of digital signal processing power, enough to process (i.e. voice and fax over IP) up to six T1 or E1 lines in real time Can be equipped with a variety of standard WAN and telephony mezzanines, including T1, E1, SCSA, and ATM Can be equipped with up to 72 100-MHz TMS320VC549 DSPs, which are implemented as six mini-PCI mezzanines A high-density DSP telecom CompactPCI board () Rugged, high performance OpenVPX DSP (digital signal processing) engine based on Intel next-generation quad-core processor technology () VPX3-453 3U VPX Virtex-68640D DSPThe VPX3-453 is a high performance, small form factor DSP engine that combines a Xilinx194174 Virtex174-6 FPGA and a Freescale174 Power Architectur e MPC8640D processor. This small form-factor 3U VPX (VITA 4648) card is ideal for SWaP-constrained environments and is designed to support the full -40 85 deg C rugged operating temperature range. The VPX3-453 speeds and simplifies the integration of advanced DSP and image processing into embedded systems designed for demanding Radar Processing, Signal Intelligence, ISR, Image Processing, and Electronic Warfare applications. () DSP-Based Data Acquisition Sub-SystemsA line of multiprocessor DSP boards and modules integrated into complete data acquisition subsystems () Designed for industrial process and control applications Deliver from 6400 MIPS fixed point DSP performance up to 16 GFLOPS floating point performance in a single 6U VMEbus or CompactPCI slot Based on Ixthos CHAMP architecture ProWare PMC-440A rugged FPGA PMC card for the capture, processing, and output of data derived from high-speed sensors such as electro-opticalinfrared (EOIR) and radar systems () Onboard FPGA delivers up to 20 billion operationssec performance for FFT and digital filter DSP functions Can be configured with either of two versions of the Xilinx Virtex-II Pro FPGA: the XC2VP20 (9,280 logic slices88 18x18 multipliers) or the XC2VP40 (19,392 logic slices192 18x18 multipliers) 64-bit, 66 MHz PCI interface with support for PCI-X CHAMP-AV5 6U VMECurtiss-Wright Controls first DSP engine with the new Intel Core i7 processor () Brin gs the floating point performance of the Intel Core i7 architecture to VME64x form factor standard Utilizing a pair of 2.53 GHz dual-core Core i7 processors, the CHAMP-AV5 delivers up to 81 GFLOPS of performance High-bandwidth PCIe architecture, featuring onboard PCIe connections between the processors and the PMCXMC sites CHAMP-XD2M 6U OpenVPX Intel Xeon D DSPThe 6U OpenVPX CHAMP-XD2M rugged Intel Xeon D module is designed for use in high memory capacity, compute-intensive Industrial, Aerospace and Defense applications, enabling developers of High Performance Embedded Computing (HPEC) systems to take full advantage of the unmatched performance of today22683648482s leading-edge Xeon processor D architecture. () CHAMP-AV IVThe third generation of our quad PowerPC DSP boards with the QuadFlow architecture providing high bandwidth connections between four 7447A7448 processors () Quad PowerPC 7447A7448 processors at up to 1.25 GHz Up to 512 MB DDR-250 SDRAM with ECC per processor (2 GB total) and 64 Kbytes L1 and 1 Mbyte (7448) L2 internal caches operating at core processor speed QuadFlow architecture with 3.2 GBs peak on-board throughput PCI v2.2-compliant, 64-bit universal PCI card () A high performance DSP board optimized for high-bandwidth, low-latency digital signal processing applications () A high performance DSP board optimized for high-bandwidth, low-latency digital signal processing applications () A TMS320C6200 DSP design suite that supports TIs eXpressDSP real-time software technology () Bit-true fixed and floating point DSP system design C code generation Integrates with Code Composer Studio for rapid prototyping A new version of SystemView that reduces design time for DSP and wir eless communications systems by providing additional modeling, analysis, and debugging features () Design and simulation ensures that the RF front-end, the AD converter, and the DSP functions will all interact together correctly Includes enhancements to SystemViews analysis and debugging capabilities A designer can trace a signal through an entire system simply by moving a virtual probe to the output of each block of the block diagram during system simulation A system-level design tool for DSP and communications applications () Provides Simulink integration, enhanced filter design tools, and a significant new offering of models for communication applications Enhanced communications library includes TDMA multiplexerdemultiplexer, OFDM modulationdemodulation, Gold Code Generator, Puncture, Depuncture, and QAM detector, mapper, demapper models The RFAnalog and DSP libraries also contain new models A universal DSP development system that allows construction of scalable DSP systems () Syste m comes in a 19-inch, 3U ruggedized enclosure with a single Atlas board The Atlas I board has two 120 MFLOPS floating-point ADSP-21060 processors The Atlas II board has two 480 MFLOPS ADSP-21160 processors Virtuoso 4.1An integrated development environment for real-time embedded systems that includes a four-layer, microkernel-based RTOS that is optimized for DSP and ASIC cores () Requires 2 Kwords to 10 Kwords of memory, and supports DSPs and RISC cores from Analog Devices, ARM, Infineon, and Texas Instruments Tool suite includes a project manager, a kernel-optimizing system generation tool, and graphical analysis and debugging tools for DSPs Scheduling options include round robin with prioritization, time-slicing, and prioritized, preemptive scheduling A universal digital signal computer () CompactPCI form factor Hosted by a Pentium running Windows NT Target system consists of one or more DSP boards with 2 ADSP-21060 (SHARC) each A TMS320C620x fixed point-based universal digital signal computer () The MSC8156 Evaluation Module (MSC8156EVM) is a cost-effective tool intended for engineers evaluating the MSC815x and MSC825x family of Freescale Digital Signal Processors (DSPs) () The MSC815x and MSC825x family of DSPs are highly integrated DSP processors that contain one, two, four or six StarCore SC3850 cores The family supports raw programmable DSP performance values ranging from 8 GMACs to 48 GMACs, with each DSP core running at 1 GHz These devices target high-bandwidth, highly computational DSP applications such as 3GPP, TD-SCDMA, 3G-LTE and WiMAX base station applications as well as aerospace and defense, medical imaging, video, voice and test and measurement applications MSC8256The MSC8256 is based on the industrys highest performance DSP core, built on StarCore technology, and designed for the advanced processing requirements and capabilities of todays high-performance, high-end industrial applications for the medical imaging, aerospace, defense and advanced test and measurement markets () It delivers industry-leading performance and power savings, leveraging 45 nm process technology in a highly integrated SoC to provide performance equivalent to a 6 GHz, single-core device. The MSC8256 will help equipment manufacturers create end products and services that integrate more functionality in a smaller hardware footprint The MSC8256 DSP delivers a high level of performance and integration, combining six new and enhanced, fully programmable SC3850 cores, each running at up to 1 GHz. The SC3850 DSP core has been independently assessed to enable 40 percent more processing capability per MHz than the nearest DSP competition A high-performance internal RISC-based QUICC Engine subsystem supports multiple networking protocols to guarantee reliable data transport over packet networks while significantly offloading processing from the DSP cores MSC8156The MSC8156 is based on the industrys highest performance DSP core, built on StarCore technology, with added performance from a Multi-Accelerator Platform Engine (MAPLE-B) for Fast Fourier Transforms (FFT), Inverse Fast Fourier Transforms (iFFT), Discrete Fourier Transforms (DFT), Inverse Discrete Fourier Transforms (iDFT) and Turbo and Viterbi decoding () The MSC8156 supports the advanced processing requirements and capabilities of todays high-performance medical, aerospace and defense and advanced test and measurement markets It delivers industry-leading performance and power savings, leveraging 45 nm process technology in a highly integrated SoC to provide performance equivalent to a 6 GHz, single-core device The MSC8156 will help equipment manufacturers create end products and services that integrate more functionality in a smaller hardware footprint A device that allows the host debug system to communicate with a Motorola DSP target system through the JTAGOnCE connector () Commands entered from the host are parsed, and a series of low level command packets are sent to the Command Converter, which, in turn, translates low level command packets into serial sequences that are transferred to the target DSP via the OnCE port The Command Converter Kit includes a Command Converter, a software development tools CD, and Command Converter product documentation Command Converters include Ethernet, PCI, Parallel, and Universal (ISASBUS). . Core SC140-based DSP with a 300 MHz DSP core Four ALUs provide 1200 DSP MIPS, 150 MHz programmable network protocol engine, 512 Kbytes of onchip SRAM, 100 MHz 64-bit or 32-bit PowerPC bus interface, and a programmable memory controller On-chip 300 MHz enhanced filter compressor and centralized DMA engine High-level application-enabling software option for fast time to market () Framework level software option adds flexibility to add algorithms and connections Board and library level software option for ultimate control Latest generation DSPs for low cost and power consumption per channel DSP56F801A DSP core based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle () Microprocessor-style programming model and optimized instruction set allow generation of efficient, compact code for both DSP-style and MCU-style applications Instruction set is highly efficient for C Compilers to enable rapid d evelopment of optimized control applications Integrated program Flash and data Flash memories A 24-bit multichannel audio decoder DSP optimized for cost-sensative consumer audio applications () Supports all of the popular multichannel audio decoding formats, including Dolby Digital Surround, Moving Picture Experts Group Standard 2 (MPEG2), and Digital Theater Systems (DTS), in a single device with sufficient MIPS resources for customer defined post-processing features such as bass management, 3D virtual surround, Lucasfilm THX5.1, soundfield processing, and advanced equalization Uses the single-instruction-per-clock-cycle DSP56300 core, while retaining code compatibility with the DSP56000 core family Contains audio-specific peripherals and an onboard software surround decoder, and is offered in 100 MHzMIPS and 120 MHzMIPS versions at 3.3V . A DSP core based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle () Microprocessor-style programming model and optimized instruction set allow generation of efficient, compact code for both DSP-style and MCU-style applications Instruction set is highly efficient for C Compilers to enable rapid development of optimized control applications Integrated program Flash and data Flash memories A StarCore-based DSP with four 300 MHz Star () Core SC140 DSP extended cores 16 ALUs onchip deliver 4,800 MMACS, 12 G RISC MIPS (Performance equivalent to a 1.2 GHz SC140 core) Four 300 MHz EFCOPs P2020-MSC8156 AdvancedMCThe Freescale P2020-MSC8156 AdvancedMC (AMC) reference design is a multi-standard baseband development platform for the next generation of wireless standards such as LTE, WiMAX, WCDMA and TD-SCDMA. () A single-chip RISC microprocessor () 32-bit RISC-type SuperH RISC engine architecture CPU with digital signal processing (DSP) extension Cache memory, on-chip XY memory, and memory management unit (MMU), as well as peripheral functions required for system configuration Includes data protection, virtual memory, and other functions provided by incorporating an MMU into a SuperH Series microprocessor (SH-1 or SH-2) USB-connected Software-Defined Digital Radio system () Ready-to-Go SystemA ready-for-use low-cost system including USB-connected programmable FPGA and DSP hardware () Includes USB-connected FPGADSP hardware of the users choice, USB cable, IO cables to interface to peripherals, main power supply unit, and CD containing software tools, examples, and documentation Connects to PCs using high-speed USB Allows users to download FPGA designs, then exchange data between the FPGA and PC at speeds up to 40 Mbps HERON DSP SystemsHERON high-performance modular signal processing systems for PCI-based, USB connected, and Embedded use are programmable and reconfigurable, using common APIs to provide compatibility and complete flexibility () Choose one or combine any number of our off-the-shelf modules Modules with Xilinx Virtex FPGA (with external memory options plus digital and analog IO choices) and TI 8216C6000 DSP Mount selected modules on a HERON module carrier which provides real-time data connections with 400 Mbps possible in each direction simultaneously HERON-IO2A FPGA module with Virtex II 1M gates plus two channels of 12-bit 125 MHz AD and two channels of 14-bit 125 MHz DA () Analog serial bandwidth of 500 MHz in and 145 MHz out When fitted to a HERON module carrier, can have its FPGA 8220program8221 downloaded from the PC over the HERON serial bus, allowing users to program and reprogram the FPGA IP available for commonly used functions HERON-FPGA12HERON module with Virtex-4FX12 FPGA plus DDR SDRAM, flash memory, and 60 bits digital IO () HERON-FPGA3A FPGA m odule with digital IO () PlugPlay PCI 2.1 33MHz32-bit slave, MasterSlave (optional) support Up to 400k gates in Spartan-3 family FPGAs Spartan-3 FPGAs system clock rate up to 320 MHz A configurable and scalable RTOS architecture for convergent processing () Uses two real-time kernels: RTXCss, and single-stack, thread-based kernel, and RTXCms, a multi-stack task-based kernel Meets the requirements of real-time, control-processing, or Digital Signal Processing (DSP) applications Supported processors: ARM 77T, 99T, Motorola DSP56F800, Motorola DSP65300600, Motorola ColdFire family, Motorola PowerPC, Motorola StarCore MSC8101, and Texas Instruments TMS320C54x, TMS320C55x . A real-time multi-tasking kernel (RTXC) for Motorolas DSP 56303307309EVM digital signal processors () Motorolas Suite56 Software Development Tools include a processor simulator, C compiler, assembler and linker, and a hardware debugger This suite of tools and RTXC form a new embedded development environment Features include: (1) small code footprint of about 1,500 to 4,500 words (2) full source code and no run-time royalties (3) support of nested interrupts (4) extensive interrupt handling models and examples (5) macros to simplify the creation of interrupt service routines (6) support for mixed assembly language and C programming and (7) a GUI-driven system generation utility that allows specification and generation of RTXC system objects without having to know the internals of the kernel objects A software development kit based on Texas Instruments TMS320DSC2 DSP () Provides developers access to the complete DSPLinux simulation and hardware environment through DevelopOnline DSPLinux is optimized for multimedia applications in which DSPs offer high processing power with low battery consumption Focused on dual-core ARMDSP architectures, with the Linux kernel residing on the ARM processor to control the operation of the DSP From Microchips PIC24 16-bit MCUs through the dsPIC 30 to the dsPIC 33, DSPnano has seamless support including CC integrated development environment (IDE), a DSP RTOS, and DSP libraries () CC IDE based on Eclipse with a highly productive user interface DSPnano operating system level simulator Seamless integration with Microchips MPLAB IDE for instruction-level simulation, compiling, and debugging using ICD2 or REAL ICE A signal processing operating system intended for small signal processors and small DSP networks () Enables adding real-time signal processing capabilities () PCI Mezzanine Card (PMC) is a widely used industry standard for small-sized mezzanine modules A high-performance DSP processor and graphical application development in LabVIEW Suitable for real-time processing applications SI-C6713DSP-PC104pAn embedded PC104-Plus DSP board () Texas Instruments TMS320C6713 DSP at 300 MHz Up to 256 MB of SDRAM using conventional 144-pin SODIMMs 2.25 W typical power consumption PCI, CompactPCI, PMC, PC104-Plus form factors () SI-C6713DSP-PCIDSP board for data acqusition, measurement, and digital control applications () SI-C33DSP-cPCIReal time software accelerator board for LabVIEW based on Texas Instruments TMS320VC33 family of floating point DSPs () SI-C6713DSP-(PCI)Real time software accelerator board for LabVIEW and Visual Basic based on TIs TMS320C6x family of floating point DSPs () DSP board for PC104-Plus () 1,800 MFLOP peak performance with C6713, 1,200 MFLOPs with C6711, 32 bit floatingfixed point precision Up to 256 MB SDRAM, using conventional PC133 SDRAM SODIMM format Full 32 bit bi-directional PCI initiated bus mastering, with 132 MBps peak transfer rate A board providing high-density DSP resources and a high level of general purpose, programmable MIPS per square mm () Compliant with 64xx IP video, transcoding, wireless, and voice algorithms Includes WinXP and Linux drivers and C code API, full DSP software, DSP with real-time examples Up to eight C6414, C6415, or C6416 DSPs A DSP board that combines a 32-bit floating-point TMS320C44 DSP with up to 512K x 32 SRAM and high-speed, multiple IO paths for connectivity to analog IO or other peripheral PC104 boards or other C4x processors () Four comm -port connectors, 32-bit 8220GlobalBus8221, and EPROM or Flash EEPROM site Supported by DSPower and Hypersignal software . SigC5502Dual DSP 24-bit audio board () Dual 300 MHz C5502 processor sites Stereo 24-bit 96 kHz audio IO, 100 dB SNR typical Single-ended and differential-ended audio connector options SigC67xx-SODIMMA quad processor DSP module () Up to four Texas Instruments C67xx processors Up to 5.4 GFLOPS 32-bit floating-point performance 4M x 32 off chip SDRAM and 64k x 32 zero-wait-state onchip SRAM per processor 300 to 480 MIPS Multiprocessor DSP Modules () 384768k x 16 SRAM Three 100 to 160 MHz C549, C5402, C5409, or C5416 cores, in three 144-pin GGU packages, each with separate 2.5v (or 1.8v) core and 3.3v peripheral voltages 128k x 16 or 256k x 16 zero-wait-state external SRAM per core A PTMC card that condenses the Texas InstrumentsTelogy Phase III High-Density VoIP reference design 8211 including DSP farm and network processor 8211 into PMC form factor () IP telephony applications include echo can farm, transcoding server, media gateway, complete soft switch solution using onboard host proce ssor, Asterisk PBX, and more Telogy software compliant OC-3 channel capacity A modular DSP resource board () Provides up to 1920 MIPS in a single PC104 form factor Accepts off-the-shelf processor modules with Texas Instruments C54xx DSPs and 16-bit audio and speech IO modules, and custom modules, for example H.110 or MVIP subset High-speed host interface Signal Ranger Mk3 is a DSP board featuring a TMS320C6424 DSP running at 590 MHz and a XC3S400 FPGA (Signal Ranger Mk3 Pro. version only) () This DSP board provides 6 analog IOs (96 kHz24-bit) It has been designed for pro-audio and high-performance control applications Communication interfaces include a high-bandwidth USB 2 interface as well as an Ethernet communication interface that allows the remote control of the DSP board over the web (an IP Stack DSP firmware is included) Signal Ranger MK2DSP: TMS320C5502 16-bit fixed point DSP, running at 300 MHz, with 32 Kwords of on-chip RAM () TIGER DSP is a digital signal processing board featuring a Xilinx Virtex 6 FPGA, data memory, and various host connections. () A 6U VMEbus board with a VME64 masterslave interface () Two processors available: single, dual, or quad 1600 MIPS, 200 MHz TMS320C6201B DSPs or single, dual, or quad 1 GFLOPS, 167 MHz MS320C6701 DSPs Up to 2 Mbytes of SBSRAM and 64 Mbytes of SDRAM Hurricane, a single chip PCI bridge optimized for DSP systems CompactPCI DSP system supports TMS320C6701 architecture () Dual or quad processor with distributed shared memory architecture provided by the Hurricane PCI-to-DSP bridge chip SBSRAM distributed shared memory Additional IO capabilities include IP Modules, PMC modules, DSP-Link 3, custom IO, and Spectrum-developed PEM modules which provide 400 Mbytessec of IO bandwidth per DSP Single-channel digital radio receiver module with software demodulation libraries () This surveillance solution combines an AD converter, digital down converter, TMS320C44 DSP processor, and a DA converter on a single-wide TIM-40 module Designed to work with Spectrums LeMans VXI product . InglistonA quad PCI DSP system based on the 250 MHz, fixed-point C6202 processor () A high-performance, programmable digital interface that connects Spectrums 8216C6000-based DSP boards to custom and standard IO systems () Provides up to 100 Mbitssec of IO bandwidth to each 8216C6000 DSP Total data throughput of 200 Mbitssec Programmed to interface to virtually any type of digital IO devices, including digital cameras, motor controllers, and as standard and custom parallel interfaces Single-channel digital radio receiver module with software demodulation libraries () This surveillance solution combines an AD converter, digital down converter, TMS320C44 DSP processor, and a DA converter on a single-wide TIM-40 module Designed to work with Spectrums LeMans VXI product . Multiplatform digital radio receiver consists of MDC44DDC 50 MHz TIM module (1 MByte or 4 MBytes), MD70MAI 70-Msamplesec AD converter TIM module, 50 KHz analog daughter module and DDR cable kit () Scaleable solution maintains interoperability with VXI, ISA, PCI and VME platforms Incoming signals from an antenna system digitized by TIM-40 based AD converter and forward via 1.4 Gbits G-Link network to one or more TIM-40 based receiverDSP blocks for demodulation and analysis Easily daisy-chained . An octal VMEbus processing engine () Eight 250300 MHz 8216C6203 fixed-point processors Peak performance of 16,00019,200 MIPS Solano-based architectures provides 200 Mbytessec full-duplex links between processors PRO-4600A 3U CompactPCI processing engine that uses a combination of FPGA, DSP, and GPP to support black-side signal processing for software defined radio (SDR) applications () 3U CompactPCI form factor Available in conduction-cooled and air-cooled versions Rugged conduction-cooled carrier versions follow the IEEE 1101.2 specification and operate with ANSI VITA 20 compliant XMC modules Barcelona-HSA 6U, hot-swap CompactPCI board combining DSP multiprocessor hardware and software tools for designing high availability systems () A DSP-based digital radio PMC mezzanine for use with Spectrums TMS320C6x-based carrier products () The PMC-MAI is a 65 M samplessec analog input PMC, the PEM-2PDC is a dual-programmable down converter module, and the PEM-4PDC is a quad-programmable down c onverter module Both PEM modules are based on Spectrums Processor Expansion Module (PEM) open specification For commercial and military signals intelligence or surveillance applications ePMC-8310A Texas Instruments TMS320C6416C6415 DSP-based multiprocessing engine for communications applications () Choice of one or two 600 MHz TMS320C6416 or TMS320C6415 fixed-point DSP processors with a peak performance of 4800 MIPS per processor Integrated Viterbi and Turbo co-processors Eight dedicated high-speed data paths to the DSPs, connected through a programmable router for dataflow reconfigurability AcceleraA graphically-driven, modular, system-level software tool, designed to speed the development of multiprocessor DSP applications for Spectrums multi-DSP TMS320C620203 products () A PCIe-based carrier card with dual XMC sites () Can be used within a PC-based system to interface to Spectrum FPGA, DSP, and IO processing engines Flexible data routing architecture, allowing numerous combinations of FPGA, DSP and GPP signal processing devices Supports applications requiring high-speed, low latency, deterministic data paths The LeMans 840 MFLOP octal TMS320C4x VXIbus master board can host up to six single-wide or four double-wide C4044 DSP modules and TIM-40 form factor SRAM, DRAM, EDRAM, or IO modules () Supports VXI shared memory, VXI masterslave modes, and 80 Mbytessec data transfers via the HP local bus Features JTAG input and output connectors, a test bus controller, and device driver support via VISA or SICL . An expansion module that connects high-speed digital signal processors (DSPs) to the Internet () Allows a sophisticated collection of DSPs to connect to EthernetInternet directly and without involvement of a host computer Uses Texas Instruments 225-MHz TMS320C6713 DSP, based on TIs high-performance, advanced VelociTI VLIW architecture NetSilicon Net-50 ARM CPU ICE105: Embedded IO Programmable SystemSUNDANCE is a worldwide supplier and manufacturer of industrial-class PCIe104 digital signal processing (DSP), configurable small form factors and COTS embedded systems. The ICE105 is a rugged system built around a complete range of PCIe104 small form factor, stackable IO-configurable and programmable solutions. () A library of floating-point DSP vectors and functions () Broad range of callable functions significantly reduces the development time of many DSP applications targeting Texas Instruments (TI) TMS320 DSP-based platforms Hand-coded and optimized functions Includes a data conversion unit that facilitates the conversion of fixed-point and integer formats into floating-point units, as well as the conversion of floating-point units into integer formats A platform for telecom, image processing, medical, and industrial systems () A CompactPCI, multi-DSP system () Four C6416, 600-MHz DSPs, with 32 MB of private SDRAM memory for each DSP Up to 800 MBps IO bandwidth per DSP Optional shared memory interface for each DSP A DSP TIM-40 mezzanine that incorporates four 60 MHz TMS320C44 DSPs, and can be used to provide up to 16 DSPs on a VMEbus carrier board () Configured with either 512 Kbytes or 2 Mbytes of SRAM per processor Memory is divided between the processors local and global buses, ensurin g optimal performance from the C44s modified Harvard architecture . SMT7005Four C6201 200MHz DSPs 16MB SDRAM 512KB SBSRAM of private memory for each DSP Up to 800Mbytess IO bandwidth per DSP Optional shared memory interface for each DSP () SMT7006Four C6701 167MHz DSPs () 16MB SDRAM 512KB SBSRAM of private memory for each DSP Over 800Mbytess IO bandwidth per DSP using Sundance Digital Bus and Datapipe Links Optional shared memory interface for each DSP Direct connection to C6000 DSP systems () High accuracy signal source through stringent design criteria communications, base stations and Zero-IF subsystems Wireless local loop (WLL) Local Multipoint Distribution Service (LMDS) A TIM mezzanine that hosts one or two TMS320C6x DSPs () Up to 32 Mbytes of onboard memory Enables a truly distributed DSP processing system The modules can be fitted to a VXI carrier board, giving performance from 1 to 8 GFLOPS when using the TMS320C6701 DSP SMT387Integrated DSP, memory, flash, and storage solution () Includes the latest generation Serial ATA controller, a 600 M Hz DSP, and Virtex-II Pro Works in an array of modules as a slave or host Can run standalone and use the on-module flash for booting and control of the disk array SMT417Conduction cooled PMCXMC card with 2 TI DSP at 1 GHz each and a Xilinx XC2VP50 FPGA and much memory () Combining a Texas Instruments TMS320DM642 DSP-based digital media processor at 720 MHz and a Xilinx Virtex-4 FX-60 FPGA, the SMT339 packs huge compute power into a small development board () Software support includes TIs Code Composer Studio Integrated Development Environment (IDE) and 3Ls Diamond FPGA Interfaces include serial ports or the Rocket Serial Link Used with a TIM carrier such as the SMT130 for PCI-104 or standalone, designers can be up and running quickly . SMT130Onboard XDS-510 compatible JTAG Master () Global bus bandwidth in excess of 100 MBps Host interface via ComPort in excess of 10 Mbps Can support multi-DSP and FPGA resources A media processing solution offering simultaneous support for Triple Play convergence voice, video, and data (faxmodem), all running on a single DSP () Suitable for equipment manufacturers who develop media gateways, CTI products, and other Media over Packet (MoP) applications Includes the SurfUP Open DSP Framework that enables integration of user-defined algorithms into the DSP, based on simple and intuitive APIs that interface with Surfs DSP software Quick integration for reduced time-to-market SurfUPDSP software components comprised of a media processing solution offering simultaneous support for Triple Play convergence (voice, video, and data (faxmodem)) all running simultaneously on a single DSP () Equipment manufacturers who develop media gateways, CTI products, and other Media-over-Packet (MoP) applica tions can integrate a specific media type into their DSP software framework and gain from Surfs robust and field-hardened enabling technologies Powered by an easy-to-use and layered API, the SurfUP DSP software components are ANSI-C compliant (with minimal assembler code for optimization) for cross platformcompiler support Field-hardened DSP software components optimized to run specifically on TIs C64xx DSP generation Fully-integrated RoHS-compliant PMCPTMC DSP resource board providing multimedia processing capabilities: voice, video, and data simultaneously () PMCPTMC form-factor DSP farm, pre-integrated with leading CompactPCI and AdvancedTCA chassis Carrierenterprise-grade, field-proven, and cost effective solution saving resources and reducing RD efforts Complete media processing package for audio, video and data (fax and modem) SurfRiderAMC-EVMComprehensive application development environment () Enables telecom applications developers to handle different DSPs Stand-alone desktop u nit simulating AdvancedTCA and MicroTCA chassis for resource-efficient telecom development environment Full DSP control and monitoring over GbE connection for reduced application development and testing time SurfRiderAMCA RoHS-compliant AdvancedMC DSP resource board, preintegrated with AdvancedTCA and MicroTCA chassis () Provides flexible yet heavy-duty multimedia processing capabilities Complete media processing package for audio, video, modem, and fax Flexible and scalable modular design supporting up to 8 TI C64x DSPs onboard SurfExpressPCIeFully integrated RoHS compliant PCIe DSP resource board providing multimedia processing capability: voice, video. and data () Graph-based Physical Synthesis fast timing closure and a push-button performance boost of up to 20 percent () RTL-based Verification Technology offers the fastest method of finding functional errors in a design thanks to simulator-like visibility into a live, running FPGA with real-world stimulus Automatic Handling of DSP functions infers DSP functions from RTL and maps into vendors DSP hardware (such as MAC) ASIC design-style support built-in gated clock conversion and a DesignWare compatible library enables ASIC code to be implemented into an FPGA without modification SPW Hardware Design System (HDS)Fastest path from innovation into implementation for digital signal processing systems, applying a model-based design approach () At its core is the C Data Flow (CDF) modeling paradigm, which enables the most efficient description of digital signal processing systems which may be implemented in dedicated digital hardware or embedded software SPW Hardware Design System (HDS) is a key component in the SPW product family It accelerates the hardware design, verification, and analysis of complex, algorithm intensive Digital Signal Processing (DSP) systems Unique Synplify DSP synthesis engine 8211 Automatically creates optimized algorithm RTL architectures from your DSP model () Powerful DSP synthesis optimizations 8211 Exploration of speedareadevice technology trade-offs without changing your DSP model Comprehensive DSP library 8211 With full multi-rate support and advanced fixed-point quantization analysis M-Control feature 8211 Enables use of M-language for concise expression of complex state machine and control logic functionality An application processor for 2.5 and 3G wireless devices () Dual core architecture optimized for efficient operating system and multimedia code execution TMS320C55x DSP provides superior multimedia performance while delivering the lowest system-level power consumption TI-enhanced ARM 925 core with an added LCD frame buffer to run co mmand and control functions and user interface applications StarterWareFree software enables quick and simple programming of TI embedded processors () user-friendly, production-ready software for Sitara2268222162 32-bit ARM194174 microprocessor (MPU), C60002268222162 digital signal processor (DSP) and DSP ARM developers provides application developers with a flexible starting point that does not require the use of an operating system allows for easy migration to other TI embedded devices A client-side telephony DSP system () Provides 14 eXpressDSP-compliant algorithms on one chip, including data, telephony, and voice algorithms For PSTN-connected products Provides an open DSPBIOS real-time kernel software framework with a complete telephony algorithm library, on-chip memory and peripherals A fixed-point, 16-bit DSP dual-core solution () Code Composer (version 3.0) includes a DSP software simulator for Texas Instruments DSPs, including the C6x () Mimics the actual execution of DSP code without the presence of a DSP chip Code Composer is an IDE that allows designers to edit, build, manage projects, debug and profile from a single application Users can: (1) compile in the background (2) analyze signals graphically (3) perform file IO (4) debug multiple processors and (5) customize the IDE via GEL A DSP family targeted toward appliances, industrial products, consumer products, automotive products, and office products () Up to 40 MIPS of processing power from the processing core Onchip Flash or ROM Dedicated peripherals, such as pulse-width modulation, ultra-fast AD converters, and CAN modules Real-time software technology that simplifies and streamlines the DSP product development process, reducing product development time () Comprised of the TMS320 DSP Algorithm Standard, a single, standard set of coding conventions and application programming interfaces (APIs) for algorithm creators to wrap the algorithm for system-ready use Includes the Code Composer Studio integrat ed development environment (IDE) Includes DSPBIOS, a scalable, real-time kernel and a growing base of TI DSP-based software modules from third parties that can be easily integrated into systems by OEMs Texas Instruments Incorporated is offering developers the industry22683648482s highest performing, scalable and flexible multicore solutions based on its TMS320C66x digital signal processor (DSP) generation. () Fixed- and floating-point capabilities Highly suited for audio infrastructure products as well as vibration and acoustic analyzers Excellent fit for high precision motion control and high channel count real-time process control system An integrated Internet audio chip () Dual Multiply and Accumulate Chip (MAC) on a DSP Embedded Universal Serial Bus (USB) capabilities Supports Secure Digital (SD), Memory Stick, Compact Flash, Smart Media, and Multimedia Card (MMC) TMS320C6472 Multicore DSPSix high speed C64X DSP cores running at 500MHz, 625MHz, 700MHz, and fully backward compatible with other C64X DSP cores () Highest performance DSP from TI with up to 4.2 GHz33600 MMACs and 4.8 MB on-chip L1L2 RAM Offers best power efficiency in the industry with 3GHz performance at 0.15mWMIPS Optimized DSP architecture maximizes subsystem performance on a chip. One of the advantages of this architecture is that in addition to dedicated L1 and L2 memory to each core, the C6472 features 768KB shared L2 programdata memory and a shared memory controller to facilitate high efficient and flexible inter DSP core communications An integrated development environment () Supports C55x and C64x DSPs Includes Visual Code Generation productivity tools, the C6000 Profile Based Compiler, and C5000 Visual Linker Project manager handles thousands of files and supports external make file capabilities to enable working across both PC and Unix Floating-point Digital Signal Processors (DSPs) () Advanced Very Long Instruction Word (VLIW) C67x DSP core L1L2 memory architecture Enhanced Direct Memory Access (EDMA) controller with 16 independent channels A digital still camera chip () TMS320C5000 DSP and ARM7TDMI RISC processor 80 MHz, 32-bit-wide SDRAM interface Programmable CCD controller supports CCDs up to 4M pixels (2K x 2K) Automatically converts ANSI-standard C programs produced by The MathWorks Simulink, DSP Blockset, and Real-Time Workshop algorithm prototyping tools into executable DSP programs () Intuitive block diagram editor models complex systems by selecting the connecting functional elements from the Simulink and DSP Blockset libraries Real-Time Workshop converts Simulink and DSP Blockset block diagram representations into C programs, which are converted into a SPOX program and compiled for the target DSP . A fully programmable DSP-based chip designed specifically for the consumer digital multimedia market () Specifically designed for multimedia applications such as digital video camcorders, PDAs, and other portable imaging and video products Can be used as a stand alone media processor or can seamlessly interface to an external CPU as a slave processor Supports multiple applications and file formats including MPEG4, JPEG, MPEG1, M-JPEG, H.263, mp3, AAC and QuickTime Multi-channel analog interfaces with a user-programmable Spartan-IIE or Virtex-II FPGA, providing developers with the means to implement FPGA-based digital signal processing solutions () Can be used as stand-alone devices with the user-programmable FPGA responsible for supporting all signal processing functionality, or as daughtercards to micro-line DSPFPGA boards A variety of multi-channel ADA configurations are supported: 2-channel 14-bit ADA with ADC sample rates up to 65 MSps 4-channel 16-bit ADA with ADC sample rates up to 2.5 MSps 12-channel ADA with ADC sample rates up to 250 KSps If the capabilities of a Texas Instruments TMS320C6000 DSP processor are required, an ORS-11x board can be fitted as a daughtercard to a TMS320C6000-based micro-line embedded DSPFPGA board ultra-compactThe ultra-compact UC1394a-1 and UC1394a-3 multi-chip modules provide Texas Instruments TMS320C5000 DSP, Spartan-II or Spartan-3 FPGA, and ready-to-use IEEE1394a FireWire communication capabilities in tiny 30 mm x 36 mm surface-mount PLCC packages () They are suitable as user-programmable DSPFPGA resources or as FireWire connectivity devices The UC1394a-1 incorporates a TMS320C5509 integer DSP, a 50 kGate Spartan-II FPGA, 8 MB of SDRAM In addition to the IO capabilities of the UC1394a-3, the UC1394a-1 provides external access to USB and four AD inputs provided by the TMS320C5509 DSP processor C32CPUA DSP resource board with a TMS320C32 DSP processor and SRAM, FLASH ROM, and the micro-line bus interface () Used as a modular co mponent in the micro-line DSP product family, which allows DSP processor, data acquisition, and IEEE 1394 (FireWire) communications modules to be combined and used together for industrial embedded DSP applications 405060 MHz TMS320C32 32-bit Floating Point DSP Processor Up to 2 Mbytes of zero-wait-state RAM or Double Low Power RAM A family of low-cost embedded DSP board configurations () TMS320C6000 DSP processor 400 Mbitsec IEEE 1394 (FireWire) communications Open architecture design with off-the-shelf and OEM data acquisition and IO options The micro-line series of embedded DSPFPGA boards provides embedded systems developers with a tightly integrated suite of programmable DSP, FPGA, and IO resources in small, stand-alone capable board formats () C6713Compact Features: 300 MHz TMS320C6713 floating-point DSP Spartan 6 (LX45, LX75, LX100 or LX150) or Virtex-II (250-kGate 500kGate, or 1MGate) FPGA up to 160 configurable digital IO pins Up to 128 MB SDRAM 8 MB fl ash ROM for DSP and FPGA boot code, as well as non-voltatile parameterdata storage Onboard 400 Mbps IEEE1394a FireWire interface RS-232 interface External access to TMS320C6713 DSP IO interfaces: 32-bit EMIF, XF01 pins, Timer inputoutput pins, McASP and McBSP ports, I2C, and HPI 120 mm x 67 mm footprintISO9001:2000 accredited production and CE certification C6713CPU Features: 300 MHz TMS320C6713 floating-point DSP 400K gate or 1M gate Spartan-3 FPGA up to 96 configurable digital IO pins 64 MB SDRAM 2 MB fl ash ROM for DSP and FPGA boot code, as well as non-voltatile parameterdata storage RS-232 interface External access to TMS320C6713 DSP IO interfaces: 32-bit EMIF, XF01 pins, Timer inputoutput pins, McASP and McBSP ports, I2C, and HPI 98 mm x 67 mm footprint ISO9001:2000 accredited production and CE certification . The micro-line series of embedded DSPFPGA boards provides embedded systems developers with a tightly integrated suite of programmable DSP, FPGA, and IO resources in small, stand-alone capable board formats. () C6412Compact Features: 720 MHz TMS320C6412 integer DSP 1M gate or 4M gate Spartan-3 FPGA up to 211 configurable IO pins Up to 128 MB SDRAM Up to 32 MB fl ash ROM for DSP and FPGA boot code, as well as non-voltatile parameterdata storage Two independent IEEE1394a FireWire interfaces for streaming data inout simultaneously 10100BASE-Tx Ethernet interface USB 2.0 and RS-232 interfaces External access to DSP Processor IO interfaces: 64-bit EMIF, XF01 pins, Timer inputoutput pins, McBSP ports, I2C, and 16-32-bit HPI 120 mm x 72 mm footprint ISO9001:2000 accredited production and CE certification C641xCPU Features: 400 MHz TMS320C6410, 500MHz TMS320C6413 or 500 MHz TMS320C6418 integer DSP 500K gate, 1.2M gate, or 1.6M gate density Xilinx Spartan8482-3E FPGA: up to 98 configurable digital IO pins Up to 64 MB SDRAM 8 MB fl ash ROM for DSP and FPGA boot code, as well as non-voltatile parameterdata storage RS-232 interface External access to DSP Procesor IO interfaces: 32-bit EMIF, XF01 pins, Timer inputoutput pins, McASP and McBSP ports, I2C, and HPI 98 mm x 67 mm footprint ISO9001:2000 accredited production and CE certification . XpressDSP-compliant TCPIP protocol stack with integrated DMA support () Easy-to-use software package that enables Ethernet and Internet communications on a wide variety of TI DSP hardware platforms: Commercial off-the-shelf hardware (micro-line embedded DSP boards) Texas Instruments development starter kits custom-designed hardware incorporating TI DSPs High communication efficiency and throughput Graphical development tools compliant with applicable Internet standards micro-line C671xProvides embedded systems developers with a tightly integrated suite of programmable DSP, FPGA, and IO resources in small, stand-alone capable board formats () Target high-performance floating-point DSP applications, using the powerful Texas Instruments TMS320C6713 DSP Incorporates up to 64 MB SDRAM, 8 MB boot program flash ROM, and an onboard, high-density 250 kGate, 500 kGate, or 1 MGate Virtex-II FPGA (optionally programmable) The FPGA greatly expands processing as well as hardware interfacing possibil ities A DSP board with onboard FPGA () Texas Instruments TMS320C6713 floating-point DSP processor at 225 MHz (up to 1800 MIPS or 1350 MFLOPS) Virtex-II FPGA (250k, 500k, or 1M gates) Dual 400 Mbitssec IEEE 1394 FireWire ports C6x11CPUA DSP resource board that combines either a fixed point TMS320C6211 or a floating point TMS320C6711 DSP Processor with SBSRAM, SDRAM, FLASH ROM, and the micro-line bus interface () Operating with the 32-bit fixed-point or floating-point TMS320C6211-150167 MHz or TMS320C6711-100150 MHz Micro-line bus, pin-compatible with the entire micro-line family Maximum performance of 1336 MIPS (C6211) or 900 MFLOPS (C6711) High-quality, single-board solution for applications requiring an embedded DSP and optionally programmable FPGA () Texas Instruments TMS320C6713 DSP 64 MB of SDRAM (128 MB SDRAM available on request), 2 MB flash ROM Optionally programmable Spartan-3 FPGA (up to 1 M gate density) Embedded DSP board () Texas Instruments TMS320C6211 or TMS320C6711 DSP U p to 2 MB of SDRAM or up to 64 MB of SDRAM Up to 512 KB flash EPROM, McBSP, and RS-232 micro-line C6x11CPUTexas Instruments TMS320C6211 or TMS320C6711 DSP () Up to 2 MB of SBRAM or up to 64 MB of SDRAM Up to 512 KB Flash EPROM, McBSP, and RS-232 Optional FireWire, Ethernet, analog and digital IO Micro-line C6713CompactStandalone and embedded-capable DSPFPGA board () Texas Instruments TMS320C6713 floating point DSP Processor 250k, 500, or 1M-gate complexity Virtex-II FPGA 400 MBps IEEE 1394 FireWire interface Standalone and embeddable DSPFPGA board () Texas Instruments TMS320C6713 floating point DSP 250 k, 500 k, or 1 M-gate complexity Virtex-II FPGA 400 Mbps IEEE 1394a FireWire interface A PCI-based FFT processor mezzanine that provides a complete development and processing platform for FFT-based DSP algorithms using DSP Architectures DSP-24 10,000 MIPS Vector DSP () An FFT processing module that provides high performance real-time FFT-based DSP algorithms () VectorWare is a software d evelopment tool for Vector-DSP-based boards () Provides all the tools to develop, simulatedebug, and deploy vector-DSP application code VectorBuilder is an optimizing compiler that generates vector microcode for the VT-5000 family of vector-DSP-based products Accepts a high-level vector instruction language known as VectorCode The VT-1420 product family consists of four products, VT-1420, VT-1423, VT-1425 and VT-1426 () The VT-1420 and VT-1426 are dual processor PMC modules and the VT-1423 and VT-1425 are single processor PMC modules All modules are targeted for DSP applications and are available with TMS320C6415 processors or TMS320C6416 processors These modules are compatible with any carrier board with a PMC compliant module site A 20,000 MIPS vector processing board that performs a 1K pt complex FFT in 21 181sec () The board is based on the 24-bit DSP-24 chip from DSP Architectures Designed for high-end market where FFT performance and data IO are important . A set of DSP PMC modules () VT-1420 dual and VT-1423 single TMS320C641516 DSP One or two TMS320C6415 or TMS320C6416 processors each with: clock speeds of up to 720 MHz 0, 16, 32, or 64 Mbytes of SDRAM 0, 1, or 2 Mbytes of FLASH Utopia level II interface on P14 An embedded VoIP gateway bridging legacy VME communications equipment to voicedata packet networks () 6U, single-slot, single-blade VMEbus configuration Offers modular feature expansion, scaling from a base T1E1J1 network interface board to a complete VoIP Media Gateway by adding DSP processor and protocol modules A DSP developers kit () Supports driver development for operating systems that are not directly supported by Voiceboard Includes source code for McBSP and API drivers, DSP software load utilities, API for remote IP or CompactPCI and VME based messaging and payload data transfer, example and test code, user manual, How to Write a MediaPro Device Driver manual, and up to 20 hours of telephone access to Device Driver techn ical support group . PTMC41PTMC41, a 240-port PTMC 2.15 DSP resource board, supported by Voiceboards broad range of off-the-shelf communications and VoIP media gateway software () DSP software libraries available for the PTMC41 include VoIP, conferencing (64 to 1,024 party), telephony functions, FAX, modems, vocoders, and RecordPlay resources For those customers desiring to integrate their own code onto the PTMC41 DSPs, Voiceboard offers a DSP Software Development Kit (SDK) including commonly needed telephony functions Will work with CPU, carrier board, or custom board that supports industry standard PICMG 2.15 PTMC specifications MediaPro resource software modules () MediaPro DSP software is downloaded into the memory of MediaPro DSP hardware Provides high-performance multi-port embedded modems and FAX servers . A high-density VME64 DSP resource board () SCSA TDM access Real-time multiprocessing of communications media datastreams Detection and generation of communications signaling tones PTMC41DSP PMC Mezzanine BoardA PTMC DSP resource board () Provides media conversion on 240 ports Flexible access to the H.110 backplane TDM bus and the carrier boards local PCI bus Real-time multiprocessing of communications media datastreams The SuperSpan VS32 is a VME 64 bus interface, software selectable T1E1J1 digital telephony network controller on a 6U board () A dual software selectable T1E1J1 span configurations, dual 100baseT connections, hot swappable, dual PTMC sites for optional DSP PMC and additional PowerPC 500 MIPS processor. The VS32 high-density dual span provides 60-port channel capacity Capabilities include play, record, call signaling tones, fax, V.22 and V.90 modem, conferencing, and VoIP packet voice through DSP PMC option SCSA backplane provides low latency switching of TDM data A DSP resource board with SCSA-bus-accessable DSP resources () Available with 24 C52 or 20 C549 fixed-point DSPs 128-Kbyte 15nsec SRAM per processor 16 Mbytes of shared DSP cache memory common to all DSPs A 240-port 6300 MIPS, DSP PMC board () Provides a full 240-port capacity for VoIP, telephony functions, T.38 Fax, V.22, V.90 modem, conferencing, or VoATM applications, including G.711 or G.723.1, G.729A, G.726 compression algorithms and G.168 long tail echo cancellation Compliant with PICMG 2.15 PTMC specifications, including access to the carrier board PCI and H.110 TDM buses 350-MIPS PowerPC 8240 executive controller supporting resource management, messaging, data buffers, TCP-UDPIP stacks, and dual redundant 100Base-T E thernet ports The SuperSpan VS34 is a VME 64 bus interface, software selectable T1E1J1 digital telephony network controller on a 6U board () A Quad software selectable T1E1J1 span configurations, dual 100baseT connections, hot swappable, dual PTMC sites for optional DSP PMC and additional PowerPC 500 MIPS processor. The VS34 high-density dual span provides 120-port channel capacity Capabilities include play, record, call signaling tones, fax, V.22 and V.90 modem, conferencing, and VoIP packet voice through DSP PMC option SCSA backplane provides low latency switching of TDM data Conference software C5441 DSP () Getting all the processing performance, memory and high-speed IO is a never ending quest for applications heavy in digital signal processing () Integrating the flexibility of programmable logic makes building a processor even more challenging The Xilinx Virtex-5 SXT platform establishes an industry record for DSP performance delivering 352 GMACs at 550MHz, while consuming 35 percent less dynamic power as compared to previous 90nm generation devices, and is the first DSP-optimized FPGA family to integrate serial transceivers The Virtex-5 SXT platform delivers the highest ratio of DSP blocks-to-logic needed for high-performance digital signal processing applications in wireless, such as WIMAX and high-definition video, such as surveillance and broadcast Avnet Virtex-6 FPGA DSP KitWireless, aerospace and defense, instrumentation and medical imaging applications continue to drive demanding performance requirements for todays sophisticated electronic systems () Due to their inherent hardware structure advantages, Xilinx FPGAs outstrip the high-end computing power of traditional digital signal processors Based on the performance leading Virtex-6 FPGAs, this DSP Kit bundles pre-validated software tools, IP and hardware into a platform that addresses even the most challenging applications With the addition of targeted reference designs, the Virtex-6 FPGA DSP kit enables users to focus on creating their own unique differentiation from the very beginning of the product development process, accelerating development for experienced users while also simplifying the adoption of FPGAs for new users Xilinx ISE Design Suite 11Logic, system, embedded and DSP domain-specific solutions () Pl anAhead8482 Design Analysis tool for optimizing performance ChipScope8482 Pro Analyzer and Serial IO Toolkit for real-time debug and verification System Generator for DSP for developing high-performance DSP systems using MathWorks products Avnet Spartan-6 FPGA DSP KitXilinx FPGAs exceed the computing power of DSPs with their inherent parallelism and offer co-processing methods of performance acceleration for signal processing () The Xilinx Spartan-6 FPGA DSP Kit integrates hardware, IP, software development tools and methodologies together into solutions that accelerate development for experienced users and simplify the adoption of FPGAs for new users With the addition of targeted reference designs, these DSP platforms enable users to focus on creating their own unique differentiation from the very beginning of the product development process This kit includes the Xilinx Spartan-6 LX150T board and allows users to quickly learn the different tool flows and design techniques involved in creating DSP centric designs with the Spartan-6 FPGA family Virtex-6 FPGA DSP KitProvides a platform for next generation products that include digital signal processing (DSP) which need to deliver more performance and flexibility with shorter development cycles and less cost and power () Out-of-the-box development solution that quickly builds confidence in developing DSP applications on FPGAs Includes a Xilinx ML605 development board including a Virtex-6 LX240T FPGA, design tools, IP, reference designs, and documentation Supports both traditional RTL and high-level design methodologies and can easily extended to include additional high-level design flows and IO daughter cards through third party partners and standardized integration . An ideal hardware platform to evaluate Xilinx FPGA in a wide range of video and imaging applications () Fully integrated and supported by the Xilinx System Generator for DSP software Utilizes high speed Ethernet hardware cosimulation capability and enables system integration, development, and verification of codecs, IP, and video algorithms in real time Comprised of a limited edition of the System Generator for DSP, Integrated Software Environment (ISE) FPGA design tool, Xilinx ML402-SX35 development board, video IO daughter card (VIODC), CMOS image sensor camera, power supply, cables, and detailed user guide and reference designs ISE Design Suite 12 software unlocks greater design productivity with breakthrough technologies for power optimization and cost () The Design Suite enables the fastest time to design completion with Xilinx Targeted Design Platforms 8211 available in four configurations aligned to user-preferred methodology logic, embedded, DSP, or system design Xilinx Targete d Design Platforms provide embedded, DSP, and hardware designers with access to an array of devices supported by open standards, common design flows, IP, and runtime platforms The ISE Design Suite offers domain-specific design environments and enables designers to meet power and performance goals with Xilinx CPLDs and FPGAs, including the new Virtex-6 and Spartan-6 families Spartan-3A DSPA DSP platform family () Xilinx XtremeDSP slice can be interconnected in creative ways on-chip Highest-performing family member provides 2,200 Gbps memory bandwidth Chips DSP48A slices can realize wide math functions, DSP filters, and complex arithmetic 8211 all at reduced power XtremeDSP DevicesThe Xilinx XtremeDSP initiative helps you develop tailored high performance DSP solutions for aerospace and defense, digital communications, multimedia, video, and imaging industries. () High-performance configurable FPGAs for DSP designs Development boards and Intellectual Property (IP) System Generator and AccelDSP design and development tools XtremeDSP SolutionStart designing using Simulink, MATLAB, or VHDL () HDLbitstream using System Generator for DSP tool Fast, parameterizable FFTs, filters, and FEC cores Free DSP software and IP core evaluations The Kintex8482-7 FPGA DSP Kit includes development boards, IO daughter cards, design tools, and reference designs, and gives designers the industry8217s largest portfolio of DSP, video, and floating-point IP blocks. () Hardware and documentation: KC705 base board with the Kintex-7 XC7K325T-FF900-2 FPGA 4DSP FMC150 high-speed ADCDAC FMC module USB, Ethernet, and MMCX RF coax cables universal power supply Downloadable schematics, BOM, and design files Documentation, including Getting Started Guide Software and IP: Full-seat ISE174 Design Suite Logic Edition, device-locked for the XC7K325T-FF900-2 FPGA CoreGen IP MathWorks174 evaluation software (MATLAB and Simulink) Targeted reference designs and tutorials Getting Started Reference Design High-performance DSP reference design . One integrated front-to-back FPGA IP catalog and design tool suite with unified interoperability () Domain specific design capture for DSP, embedded and logical design Accelerated system development via customization and integrated libraries of optimized IP Design tools optimized to minimize area while maximizing performance for Virtex-5 and Spartan-3 family Platform FPGAs Virtex-4 FPGAs for highest performance DSP () Up to 512, 500 MHz XtremeDSP Slices (18 x 18 multiply, 48-bit add) Virtex-4 for lowest power per channel 8211 each XtremeDSP Slice consumes only 2.3 mW per 100 MHz XtremeDSP Development ToolsModel and design your system using MATLAB, Simulink, and blocksets from The MathWorks () Use the Xilinx bit and cycle accurate library for designing algorithms for the FPGA Import MATLAB algorithms like linear algebra and matrix inversion and multiplication Automatically generate HDL or a bitstream at the push of a button with no loss in performance over designs written in HDL Power s upply 100-240 V, 5060 Hz with universal plug adaptors USB Platform download cable for configuration and debug System Generator for DSP design softwareDocumentation Fading Channels Overview of Fading Channels Using Communications System Toolboxx2122 you can implement fading channels using objects or blocks. Rayleigh and Rician fading channels are useful models of real-world phenomena in wireless communications. These phenomena include multipath scattering effects, time dispersion, and Doppler shifts that arise from relative motion between the transmitter and receiver. This section gives a brief overview of fading channels and describes how to implement them using the toolbox. The figure below depicts direct and major reflected paths between a stationary radio transmitter and a moving receiver. The shaded shapes represent reflectors such as buildings. The major paths result in the arrival of delayed versions of the signal at the receiver. In addition, the radio signal undergoes scattering on a local scale for each major path. Such local scattering is typically characterized by a large number of reflections by objects near the mobile. These irresolvable components combine at the receiver and give rise to the phenomenon known as multipath fading . Due to this phenomenon, each major path behaves as a discrete fading path. Typically, the fading process is characterized by a Rayleigh distribution for a nonline-of-sight path and a Rician distribution for a line-of-sight path. The relative motion between the transmitter and receiver causes Doppler shifts. Local scattering typically comes from many angles around the mobile. This scenario causes a range of Doppler shifts, known as the Doppler spectrum . The maximum Doppler shift corresponds to the local scattering components whose direction exactly opposes the mobiles trajectory. Implement Fading Channel Using an Object A baseband channel model for multipath propagation scenarios that you implement using objects includes: N discrete fading paths, each with its own delay and average power gain. A channel for which N 1 is called a frequency-flat fading channel . A channel for which N gt 1 is experienced as a frequency-selective fading channel by a signal of sufficiently wide bandwidth. A Rayleigh or Rician model for each path. Default channel path modeling using a Jakes Doppler spectrum, with a maximum Doppler shift that can be specified. Other types of Doppler spectra allowed (identical or different for all paths) include: flat, restricted Jakes, asymmetrical Jakes, Gaussian, bi-Gaussian, and rounded. If the maximum Doppler shift is set to 0 or omitted during the construction of a channel object, then the object models the channel as static (i.e. fading does not evolve with time), and the Doppler spectrum specified has no effect on the fading process. Some additional information about typical values for delays and gains is in Choose Realistic Channel Property Values Implement Fading Channel Using a Block The Channels block library includes Rayleigh and Rician fading blocks that can simulate real-world phenomena in mobile communications. These phenomena include multipath scattering effects, as well as Doppler shifts that arise from relative motion between the transmitter and receiver. Note To model a channel that involves both fading and additive white Gaussian noise, use a fading channel block connected in series with the AWGN Channel block, where the fading channel block comes first. The table below indicates the situations in which each fading channel block is appropriate. In the case of multiple major reflected paths, a single instance of the Multipath Rayleigh Fading Channel block can model all of them simultaneously. The number of paths that the block uses is the length of either the Delay vector or the Gain vector parameter, whichever length is larger. (If both of these parameters are vectors, they must have the same length if exactly one of these parameters is a scalar, the block expands it into a vector whose size matches that of the other vector parameter.) Choosing appropriate block parameters for your situation is important. For more details about the parameters of fading channel blocks, see The Choose Realistic Channel Property Values section under Configuring Channel Objects in the Communications System Toolbox documentation Compensate for Fading Response A communication system involving a fading channel usually requires component(s) that compensate for the fading response. Typical approaches to compensate for fading include: Differential modulation or a one-tap equalizer helps compensate for a frequency-flat fading channel. See the M-DPSK Modulator Baseband block Help page or the example in Compare Empirical Results to Theoretical Results for information about implementing differential modulation. An equalizer with multiple taps helps compensate for a frequency-selective fading channel. See Equalization for more information. The Communications Link with Adaptive Equalization example illustrates why compensating for a fading channel is necessary. Visualize a Fading Channel You can plot a fading channels characteristics using channel visualization tools. For communication systems that you implement using objects, see Channel Visualization . For communication systems that you implement using blocks, there are two ways to visualize fading channel response. One way is to double-click the block during a simulation. The second way is to select Open channel visualization at start of simulation in the block dialog box. Methodology for Simulating Multipath Fading Channels: The Rayleigh and Rician multipath fading channel simulators in Communications System Toolbox use the band-limited discrete multipath channel model of section 9.1.3.5.2 in 1. This implementation assumes that the delay power profile and the Doppler spectrum of the channel are separable 1. The multipath fading channel is therefore modeled as a linear finite impulse-response (FIR) filter. Let denote the set of samples at the input to the channel. Then the samples at the output of the channel are related to through: y i x2211 n x2212 N 1 N 2 s i x2212 n g n where is the set of tap weights given by: g n x2211 k 1 K a k sinc x03C4 k T s x2212 n ,x00A0 x2212 N 1 x2264 n x2264 N 2 In the equations above: T s is the input sample period to the channel. . where 1 x2264 k x2264 K. is the set of path delays. K is the total number of paths in the multipath fading channel. . where 1 x2264 k x2264 K. is the set of complex path gains of the multipath fading channel. These path gains are uncorrelated with each other. N 1 and N 2 are chosen so that g n is small when n is less than x2212 N 1 or greater than N 2. Two techniques, filtered Gaussian noise and sum-of-sinusoids, are used to generate the set of complex path gains, a k . Each path gain process a k is generated by the following steps: Filtered Gaussian Noise Technique A complex uncorrelated (white) Gaussian process with zero mean and unit variance is generated in discrete time. The complex Gaussian process is filtered by a Doppler filter with frequency response H ( f ) S ( f ). where S ( f ) denotes the desired Doppler power spectrum. The filtered complex Gaussian process is interpolated so that its sample period is consistent with that of the input signal. A combination of linear and polyphase interpolation is used. Mutually uncorrelated Rayleigh fading waveforms are generated using the method described in 2. where i 1 corresponds to the in-phase component and i 2 corresponds to the quadrature component. z k ( t ) x03BC k ( 1 ) ( t ) j x03BC k ( 2 ) ( t ). x2003 k 1. 2. x2026. K x03BC k ( i ) ( t ) 2 N k x2211 n 1 N k cos ( 2 x03C0 f k. n ( i ) t x03B8 k. n ( i ) ). x2003 i 1. 2 N k specifies the number of sinusoids used to model a single path. f k. n ( i ) is the discrete Doppler frequency and is calculated for each sinusoid component within a single path. x03B8 k. n ( i ) is the phase of the n th component of x03BC k ( i ) and is an i.i.d. random variable having a uniform distribution over the interval ( 0. 2 x03C0 . t is the fading process time. The discrete Doppler frequencies, f k. n ( i ). with maximum shift f max are given by f k. n ( i ) f max cos ( x03B1 k. n ( i ) ) f max cos x03C0 2 N k ( n x2212 1 2 ) x03B1 k. 0 ( i ) x03B1 k. 0 ( i ) x225C ( x2212 1 ) i x2212 1 x03C0 4 N k x22C5 k K 2. x2003 i 1. x2009 2 x2009 x2009 and x2009 x2009 k 1. 2. x2026. K In order to advance the fading process in time, an initial time parameter, t init . is introduced. The fading waveforms become x03BC k ( i ) ( t ) 2 N k x2211 n 1 N k cos ( 2 x03C0 f k. n ( i ) ( t t i n i t ) x03B8 k. n ( i ) ). x2003 i 1. 2 When t init 0, the fading process starts at time zero. A positive value of t init advances the fading process relative to time zero while maintaining its continuity. Channel fading samples are generated using the GMEDS 1 2 algorithm. Calculate Complex Coefficients The complex process resulting from either techniq ue, z k. is scaled to obtain the correct average path gain. In the case of a Rayleigh channel, the fading process is obtained as: a k x03A9 k z k x03A9 k E a k 2 In the case of a Rician channel, the fading process is obtained as: a k x03A9 k z k K r. k 1 K r. k K r. k 1 e j ( 2 x03C0 f d. L O S. k t x03B8 L O S. k ) where K r. k is the Rician K-factor of the k-th path, f d. L O S. k is the Doppler shift of the line-of-sight component of the k-th path (in Hz), and x03B8 L O S. k is the initial phase of the line-of-sight component of the k-th path (in rad). At the input to the band-limited multipath channel model, the transmitted symbols must be oversampled by a factor at least equal to the bandwidth expansion factor introduced by pulse shaping. For example, if sinc pulse shaping is used, for which the bandwidth of the pulse-shaped signal is equal to the symbol rate, then the bandwidth expansion factor is 1, and at least one sample per symbol is required at the input to the channel. If a raised cosine (RC) filter with a factor in excess of 1 is used, for which the bandwidth of the pulse-shaped signal is equal to twice the symbol rate, then the bandwidth expansion factor is 2, and at least two samples per symbol are required at the input to the channel. For additional information, see the article A Matlab-based Object-Oriented Approach to Multipath Fading Channel Simulation . located on MATLAB x00AE Central. References 1 Jeruchim, M. C. Balaban, P. and Shanmugan, K. S. Simulation of Communication Systems . Second Edition, New York, Kluwer AcademicPlenum, 2000. 2 Paumltzold, Matthias, Cheng-Xiang Wang, and Bjorn Olav Hogstand. Two New Sum-of-Sinusoids-Based Methods for the Efficient Generation of Multiple Uncorrelated Rayleigh Fading Waveforms. IEEE Transactions on Wireless Communications . Vol. 8, Number 6, 2009, pp. 312282113131. Specify Fading Channels Communications System Toolbox models a fading channel as a linear FIR filter. Filtering a signal using a fading channel involves these steps: Create a channel object that describes the channel that you want to use. A channel object is a type of MATLAB variable that contains information about the channel, such as the maximum Doppler shift. Adjust properties of the channel object, if necessary, to tailor it to your needs. For example, you can change the path delays or average path gains. Note: Setting the maximum path delay greater than 100 samples may generate an 8216Out of memory error. Apply the channel object to your signal using the filter function. This section describes how to define, inspect, and manipulate channel objects. The topics are: Select Your Country
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